[coreboot-gerrit] [S] Change in coreboot[master]: [UNTESTED] vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPI...

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74375 )

Change subject: [UNTESTED] vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case
......................................................................

[UNTESTED] vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS case

When a mainboard selects ACPI_SOC_NVS and CHROMEOS, CHROMEOS_NVS will be
selected. This causes vc/google/chromeec/acpi/chromeos.asl to be
included in the DSDT and chromeos_acpi_gpio_generate to be called when
generating the coreboot SSDT. When a mainboard also uses
DECLARE_NO_CROS_GPIOS(), this will cause variant_cros_gpio.count to be 0
and variant_cros_gpio.gpios to be NULL. chromeos_acpi_gpio_generate only
checked if the GPIO table was non-NULL, which caused the function to
exit early and not generate the OIPG package which causes the kernel to
complain about referencing the non-existing OIPG package. To avoid this,
only exit in the GPIO table pointer being NULL case if the number of
GPIOs is non-0.

TEST=None

Signed-off-by: Felix Held 
Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7
---
M src/vendorcode/google/chromeos/acpi.c
1 file changed, 25 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/74375/1

diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c
index 801f33d..fb6d0a5 100644
--- a/src/vendorcode/google/chromeos/acpi.c
+++ b/src/vendorcode/google/chromeos/acpi.c
@@ -14,7 +14,7 @@

num = variant_cros_gpio.count;
    gpios = variant_cros_gpio.gpios;
-	if (!gpios)
+	if (num && !gpios)
    	return;

acpigen_write_scope("\");