[coreboot-gerrit] Change in coreboot[master]: soc/qualcomm/qcs405: Handle unknown QUP and BLSP

[Jacob Garber (Code Review)]

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34523 )

Change subject: soc/qualcomm/qcs405: Handle unknown QUP and BLSP
......................................................................

soc/qualcomm/qcs405: Handle unknown QUP and BLSP

Print an error message and return if an unknown QUP or BLSP is
encountered. This prevents a possible null dereference of spi_clk.

Change-Id: I374e15ce899c651df9c2d3e0f1ec646e33d4bdb2
Signed-off-by: Jacob Garber 
Found-by: Coverity CID 1401086
---
M src/soc/qualcomm/qcs405/clock.c
1 file changed, 8 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/34523/1

diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c
index de42147..eae1644 100644
--- a/src/soc/qualcomm/qcs405/clock.c
+++ b/src/soc/qualcomm/qcs405/clock.c
@@ -235,12 +235,16 @@
    		spi_clk = (struct qcs405_clock *)
    				&gcc->blsp1_qup4_spi_clk;
    		break;
+		default:
+			printk(BIOS_ERR, "QUP %d not supported\n", qup);
+			return;
    	}
-	} else if (blsp == 2)
+	} else if (blsp == 2) {
    	spi_clk = (struct qcs405_clock *)&gcc->blsp2_qup0_spi_clk;
-
-	else
-		printk(BIOS_ERR, "BLSP%d not supported\n", blsp);
+	} else {
+		printk(BIOS_ERR, "BLSP %d not supported\n", blsp);
+		return;
+	}

clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg));
 }