Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75931?usp=email )
(
2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDS ......................................................................
meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDS
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to `SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS version 1.3.1 (doc number: 640228).
With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the same package.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931 Reviewed-by: Kapil Porwal kapilporwal@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Reviewed-by: Jakub Czapiga jacz@semihalf.com --- M src/mainboard/google/rex/Kconfig M src/mainboard/intel/mtlrvp/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/romstage/fsp_params.c 4 files changed, 11 insertions(+), 7 deletions(-)
Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Jakub Czapiga: Looks good to me, approved Kapil Porwal: Looks good to me, approved
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 0fb4176..407cccc 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -39,7 +39,7 @@ select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS select MEMORY_SOLDERDOWN - select SOC_INTEL_METEORLAKE_U_P + select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index e27eed9..8a59085 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -19,7 +19,7 @@ select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU - select SOC_INTEL_METEORLAKE_U_P + select SOC_INTEL_METEORLAKE_U_H
config BOARD_INTEL_MTLRVP_P select BOARD_INTEL_MTLRVP_COMMON diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 0bcbcf2..7e1353a 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -5,18 +5,22 @@ type using the `SOC_INTEL_METEORLAKE_*` options instead of selecting this option directly.
-config SOC_INTEL_METEORLAKE_U_P +config SOC_INTEL_METEORLAKE_U_H bool select SOC_INTEL_METEORLAKE help - Choose this option if your mainboard has a MTL-U (15W) or MTL-P (28W) SoC. - Note, MTL-U/P SoC combines Compute, GFX, SoC and IOE die. + Choose this option if your mainboard has a MTL-U (9W or 15W) + or MTL-H (28W or 45W) SoC. + + Note, the MTL-U/H-Processor Line offered in a 1-Chip Platform + that includes the Compute, SOC, GT, and IOE tile on the same + package.
config SOC_INTEL_METEORLAKE_S bool select SOC_INTEL_METEORLAKE help - Choose this option if your mainboard has a MTL-S (45W) SoC. + Choose this option if your mainboard has a MTL-S (35W or 65W) SoC. Note, MTL-S SoC combines Compute, GFX, SoC, IOE and PCH die.
if SOC_INTEL_METEORLAKE diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index bdc4f7a..40b7c47 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -73,7 +73,7 @@ }
/* PCIE ports */ - if (CONFIG(SOC_INTEL_METEORLAKE_U_P)) { + if (CONFIG(SOC_INTEL_METEORLAKE_U_H)) { m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table()); m_cfg->PchPcieRpEnableMask = 0; /* Don't care about PCH PCIE RP Mask */ pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp,