[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely

[Uwe Poeche (Code Review)]

Attention is currently required from: Johannes Hahn, Mario Scheithauer, Werner Zeh.

Uwe Poeche has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email )

Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
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Patch Set 3: Code-Review+1

(1 comment)

Patchset:

PS3: 
I started our ci (with activated apl1/4 and ehl1 mainboards) with that patch on top and checked on ehl1 MSR 0x610 in OS before and after the patch. Result is as regarded. The effort to set ehl1 to power limit and also verify that MSR 0x196 Bit 10 was set before and after the patch not set was interrupted.
The error which shows siemens-bot via his submit is caused by the known problematic upstream patch CB:84833 and has no correlation with the patch here.