[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S

[Michał Żygowski (Code Review)]

Attention is currently required from: Michał Żygowski.
Hello build bot (Jenkins), Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63460

to look at the new patch set (#3).

Change subject: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
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soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S

According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for
PCH-S.

Signed-off-by: Michał Żygowski 
Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/63460/3