Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.
EricKY Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68649 )
Change subject: soc/amd/mendocino: Expand DPTC_INPUT input value ......................................................................
soc/amd/mendocino: Expand DPTC_INPUT input value
Expand DPTC_INPUT value
BRANCH=none BUG=b:232946420 TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng ericky_cheng@compal.corp-partner.google.com Change-Id: I6d6a00f0eca0b0941860b9bc75da41d7a10d60e8 --- M src/soc/amd/mendocino/root_complex.c 1 file changed, 127 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/68649/1
diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 6768613..d5a457c 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +a/* SPDX-License-Identifier: GPL-2.0-only */
/* TODO: Check if this is still correct */
@@ -18,15 +18,18 @@ #include <stdint.h> #include "chip.h"
-#define DPTC_TOTAL_UPDATE_PARAMS 7 +#define DPTC_TOTAL_UPDATE_PARAMS 15
struct dptc_input { uint16_t size; struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; } __packed;
+ #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow, \ - _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit) \ + _vrmCurrentLimit, _vrmMaxCurrentLimit, _vrmSocCurrentLimit, \ + _sttMinLimit, _sttM1, _sttM2, _sttCApu, \ + _sttSkinTempLimit, stt_AlphaApu,_sttErrCoeff, _sttErrRateCoeff) \ { \ .size = sizeof(struct dptc_input), \ .params = { \ @@ -55,8 +58,36 @@ .value = _vrmMaxCurrentLimit, \ }, \ { \ - .id = ALIB_DPTC_VRM_SOC_CURRENT_LIMIT_ID, \ - .value = _vrmSocCurrentLimit, \ + .id = ALIB_DPTC_STT_MIN_LIMIT_ID, \ + .value = _sttMinLimit, \ + }, \ + { \ + .id = ALIB_DPTC_STT_M1_ID, \ + .value = _sttM1, \ + }, \ + { \ + .id = ALIB_DPTC_STT_M2_ID, \ + .value = _sttM2, \ + }, \ + { \ + .id = ALIB_DPTC_STT_C_APU_ID, \ + .value = _sttCApu, \ + }, \ + { \ + .id = ALIB_DPTC_STT_SKIN_TEMPERATURE_LIMIT_APU_ID, \ + .value = _sttSkinTempLimit, \ + }, \ + { \ + .id = ALIB_DPTC_STT_ALPHA_APU_ID, \ + .value = stt_AlphaApu, \ + }, \ + { \ + .id = ALIB_DPTC_STT_ERROR_COEFF_ID, \ + .value = _sttErrCoeff, \ + }, \ + { \ + .id = ALIB_DPTC_STT_ERROR_RATE_COEFF_ID, \ + .value = _sttErrRateCoeff, \ }, \ }, \ } @@ -200,6 +231,15 @@ { const struct soc_amd_mendocino_config *config = config_of_soc();
+uint16_t stt_m1_B; + uint16_t stt_m2_B; + uint16_t stt_c_apu_B; + uint16_t stt_skin_temp_apu_B; + uint16_t stt_alpha_apu_B; + uint16_t stt_error_coeff_B; + uint16_t stt_error_rate_coefficient_B; +_sttMinLimit, _sttM1, _sttM2, _sttCApu, \ + _sttSkinTempLimit, stt_AlphaApu,_sttErrCoeff, _sttErrRateCoeff) \ /* Normal mode DPTC values. */ struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, config->sustained_power_limit_mW, @@ -207,7 +247,16 @@ config->slow_ppt_limit_mW, config->vrm_current_limit_mA, config->vrm_maximum_current_limit_mA, - config->vrm_soc_current_limit_mA); + config->vrm_soc_current_limit_mA, + config->stt_min_limit, + config->stt_m1, + config->stt_m2, + config->stt_c_apu, + config->stt_skin_temp_apu, + config->stt_alpha_apu, + config->stt_error_coeff, + config->stt_error_rate_coefficient + ); acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
/* Low/No Battery */ @@ -221,6 +270,62 @@ config->vrm_soc_current_limit_throttle_mA); acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, sizeof(no_battery_input)); + + + struct dptc_input thermal_B_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_B, + config->sustained_power_limit_mW_B, + config->fast_ppt_limit_mW_B, + config->slow_ppt_limit_mW_B, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_B((uint8_t *)&thermal_B_input, + sizeof(thermal_B_input)); + + struct dptc_input thermal_C_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_C, + config->sustained_power_limit_mW_C, + config->fast_ppt_limit_mW_C, + config->slow_ppt_limit_mW_C, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_C((uint8_t *)&thermal_C_input, + sizeof(thermal_C_input)); + + struct dptc_input thermal_D_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_D, + config->sustained_power_limit_mW_D, + config->fast_ppt_limit_mW_D, + config->slow_ppt_limit_mW_D, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_D((uint8_t *)&thermal_D_input, + sizeof(thermal_D_input)); + + struct dptc_input thermal_E_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_E, + config->sustained_power_limit_mW_E, + config->fast_ppt_limit_mW_E, + config->slow_ppt_limit_mW_E, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_E((uint8_t *)&thermal_E_input, + sizeof(thermal_E_input)); + + struct dptc_input thermal_F_input = DPTC_INPUTS( + config->thermctl_limit_degreeC_F, + config->sustained_power_limit_mW_F, + config->fast_ppt_limit_mW_F, + config->slow_ppt_limit_mW_F, + config->vrm_current_limit_mA, + config->vrm_maximum_current_limit_mA, + config->vrm_soc_current_limit_mA); + acpigen_write_alib_dptc_thermal_F((uint8_t *)&thermal_F_input, + sizeof(thermal_F_input)); }
static void root_complex_fill_ssdt(const struct device *device)