Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43307 )
Change subject: soc/amd/common: Allow the SPI base to be set for psp_verstage ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43307/2/src/soc/amd/common/block/sp... File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/43307/2/src/soc/amd/common/block/sp... PS2, Line 23: spi_base = lpc_get_spibase();
Please make it so that garbage-collection can throw this out. […]
b/156305600 | AMD/Picasso: Enable a mechanism for using different BARs on PSP v/s x86 On x86, all controllers have a fixed base address for MMIO. However, for the PSP the base address is not fixed and instead depends on the virtual address space mapping done by the PSP BL. We are currently adding -psp.c / _psp.c which shouldn't really be required.