Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58082 )
Change subject: src/soc to src/superio: Fix spelling errors. ......................................................................
src/soc to src/superio: Fix spelling errors.
These issues were found and fixed by codespell, a useful tool for finding spelling errors.
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e --- M src/soc/amd/cezanne/fch.c M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fch.c M src/soc/amd/picasso/include/soc/platform_descriptors.h M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/cavium/cn81xx/bootblock_custom.S M src/soc/intel/alderlake/acpi/tcss.asl M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/northcluster.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/chip.h M src/soc/intel/common/Makefile.inc M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/usb4/Kconfig M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/quark/Kconfig M src/soc/intel/quark/chip.h M src/soc/intel/quark/include/soc/QuarkNcSocId.h M src/soc/intel/quark/reg_access.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/tigerlake/acpi/tcss.asl M src/soc/intel/xeon_sp/util.c M src/soc/mediatek/common/include/soc/eint_event.h M src/soc/mediatek/common/mmu_operations.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/pll.c M src/soc/mediatek/mt8195/pll.c M src/soc/nvidia/tegra124/chip.h M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra210/Kconfig M src/soc/nvidia/tegra210/Makefile.inc M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/include/soc/addressmap.h M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/sdram.c M src/soc/qualcomm/ipq40xx/gpio.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq806x/gpio.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/spi.c M src/soc/qualcomm/sc7180/display/dsi_phy.c M src/soc/samsung/exynos5250/dmc_init_ddr3.c M src/soc/samsung/exynos5250/include/soc/gpio.h M src/soc/samsung/exynos5420/dmc_init_ddr3.c M src/soc/sifive/fu540/ux00ddr.h M src/southbridge/amd/agesa/hudson/acpi/fch.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl M src/southbridge/amd/pi/hudson/acpi/fch.asl M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82371eb/acpi_tables.c M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/pch.h M src/superio/acpi/pnp_config.asl M src/superio/ite/it8772f/it8772f.h M src/superio/winbond/w83627hf/acpi/superio.asl 76 files changed, 93 insertions(+), 93 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/58082/1
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 80ce946..ac79cc9 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -127,7 +127,7 @@ pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); }
-/* configure the genral purpose PCIe clock outputs according to the devicetree settings */ +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { const struct soc_amd_cezanne_config *cfg = config_of_soc(); diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index e948bca..292cdd8 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -29,7 +29,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 6389830..4fcd3f7 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -22,7 +22,7 @@ uint8_t sq_rx_tune; /* FS/LS Source Impedance Adjustment. Range 0 - 0xF */ uint8_t tx_fsls_tune; - /* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */ + /* HS Transmitter Pre-Emphasis Current Control. Range 0 - 0x3 */ uint8_t tx_pre_emp_amp_tune; /* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */ uint8_t tx_pre_emp_pulse_tune; @@ -99,7 +99,7 @@ * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. * For example, should we need I2C0 and I2C3 have their peripheral - * devices reseted by toggling SCL, use: + * devices reset by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ diff --git a/src/soc/amd/picasso/fch.c b/src/soc/amd/picasso/fch.c index 711091c..44acc81 100644 --- a/src/soc/amd/picasso/fch.c +++ b/src/soc/amd/picasso/fch.c @@ -175,7 +175,7 @@ write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val); }
-/* configure the genral purpose PCIe clock outputs according to the devicetree settings */ +/* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { const struct soc_amd_picasso_config *cfg = config_of_soc(); diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h index 28062b6..2ea35a9 100644 --- a/src/soc/amd/picasso/include/soc/platform_descriptors.h +++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h @@ -7,7 +7,7 @@ #include <platform_descriptors.h> #include <FspsUpd.h>
-/* These tempory macros apply to emmc0_mode field in FSP_S_CONFIG. +/* These temporary macros apply to emmc0_mode field in FSP_S_CONFIG. * TODO: Remove when official definitions arrive. */ #define SD_DISABLE 0 #define SD_LOW_SPEED 1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 78ce889..f7ea782 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -56,7 +56,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 82c5437..b870bae 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -46,7 +46,7 @@ * If sb_reset_i2c_peripherals() is called, this devicetree register * defines which I2C SCL will be toggled 9 times at 100 KHz. * For example, should we need I2C0 and I2C3 have their peripheral - * devices reseted by toggling SCL, use: + * devices reset by toggling SCL, use: * * register i2c_scl_reset = (GPIO_I2C0_SCL | GPIO_I2C3_SCL) */ diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d80aeb2..d5231ad 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -400,19 +400,19 @@ reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
/* - * 0x100000 (1MiB) -> low top useable RAM + * 0x100000 (1MiB) -> low top usable RAM * cbmem_top() accounts for low UMA and TSEG if they are used. */ ram_resource(dev, idx++, (1 * MiB) / KiB, (mem_useable - (1 * MiB)) / KiB);
- /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */ + /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_resource(dev, idx++, mem_useable / KiB, (tom.lo - mem_useable) / KiB);
/* If there is memory above 4GiB */ if (high_tom.hi) { - /* 4GiB -> high top useable */ + /* 4GiB -> high top usable */ if (uma_base >= (4ull * GiB)) high_mem_useable = uma_base; else @@ -422,7 +422,7 @@ ram_resource(dev, idx++, (4ull * GiB) / KiB, ((high_mem_useable - (4ull * GiB)) / KiB));
- /* High top useable RAM -> high top RAM */ + /* High top usable RAM -> high top RAM */ if (uma_base >= (4ull * GiB)) { reserved_ram_resource(dev, idx++, uma_base / KiB, uma_size / KiB); diff --git a/src/soc/cavium/cn81xx/bootblock_custom.S b/src/soc/cavium/cn81xx/bootblock_custom.S index 03d91da..318c4d7 100644 --- a/src/soc/cavium/cn81xx/bootblock_custom.S +++ b/src/soc/cavium/cn81xx/bootblock_custom.S @@ -130,7 +130,7 @@ thunder1_cache_setup: /** * Setup L2 cache to allow secure access to all of the address space - * thunder1 compability list: + * thunder1 compatibility list: * - CN81XX * - CN83XX * - CN88XX diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 82cbad63..81c2432 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -511,7 +511,7 @@ TACK, 1, /* [16:16] IOM Acknowledge bit */ DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ /* display is OFF, clear otherwise */ - Offset(0x70), /* Pyhsical addr is offset 0x70. */ + Offset(0x70), /* Physical addr is offset 0x70. */ IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ } diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 6a71900..f6b337c 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -18,7 +18,7 @@ Offset(0xB4), BGSM, 32, /* Base of Graphics Stolen Memory */ Offset(0xBC), - TLUD, 32, /* Top of Low Useable DRAM */ + TLUD, 32, /* Top of Low Usable DRAM */ } }
@@ -58,7 +58,7 @@ * PCI MMIO Region (TOLUD - PCI extended base MMCONF) * This assumes that MMCONF is placed after PCI config space, * and that no resources are allocated after the MMCONF region. - * This works, sicne MMCONF is hardcoded to 0xe00000000. + * This works, since MMCONF is hardcoded to 0xe00000000. */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1c92b89..c4d7977 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -119,7 +119,7 @@
/* * Poll for bit 8 to check if PCODE has completed its action - * in reponse to BIOS Reset complete. + * in response to BIOS Reset complete. * We wait here till 1 ms for the bit to get set. */ stopwatch_init_msecs_expire(&sw, 1); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index e5c003a..dca95e3 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -136,7 +136,7 @@ bool "Use a binary refcode blob instead of native ModPHY init" default n help - Use the ChromeBook refcode to intitialize high-speed PHYs instead of + Use the ChromeBook refcode to initialize high-speed PHYs instead of native code.
if HAVE_REFCODE_BLOB diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index b7ddee4..76d532b5 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -93,7 +93,7 @@ if (fsp_reserved_memory_area) { fsp_res_base_k = RES_IN_KiB((unsigned int)fsp_reserved_memory_area); } else { - /* If no FSP reserverd area */ + /* If no FSP reserved area */ fsp_res_base_k = tseg_base_k; }
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index fbd7aea..f02e810 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -23,7 +23,7 @@ Broadwell can either start verstage in a separate stage right after the bootblock has run or it can start it after romstage for compatibility reasons. - Broadwell however uses a mrc.bin to initialse memory which + Broadwell however uses a mrc.bin to initialize memory which needs to be located at a fixed offset. Therefore even with a separate verstage starting after the bootblock that same binary is used meaning a jump is made from RW to the RO region diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b8dfafd..774b526 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -436,7 +436,7 @@ * * In general descriptor provides option to set default cpu flex ratio. * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. - * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0. + * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. * * Only override CPU flex ratio if don't want to boot with non-turbo max. */ diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 56e3336..ad987dd 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -41,7 +41,7 @@ # $(3) is file type, efi for test names (all .EFI files under $(MMA_BLOBS_PATH)/tests ) # , mma for test param (all .BIN files under $(MMA_BLOBS_PATH)/configs/<test name>) # -# $(MMA_BLOBS_PATH)/tests/<testX>.efi has coresponding test params +# $(MMA_BLOBS_PATH)/tests/<testX>.efi has corresponding test params # at $(MMA_BLOBS_PATH)/configs/<testX>/<XYZ>.bin #
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index f0c3149..cac7854 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -545,7 +545,7 @@
/* * Calculate the SF Mask 1: - * 1. Calcuate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0] + * 1. Calculate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0] * 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: SFWayCnt = SFWayCnt / 2 * 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - IA32_CR_SF_QOS_MASK_2 */ diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 843071e..93de2ec 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -325,7 +325,7 @@ "Only 32MiB windows are supported for extended BIOS!"); #endif
- /* Confgiure DMI Source decode for Extended BIOS Region */ + /* Configure DMI Source decode for Extended BIOS Region */ if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, soc_get_spi_dmi_destination_id()) == CB_ERR) return; diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index 97d63af..c07c96c 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -130,7 +130,7 @@ struct tcss_mux_info { bool dp; /* DP connected */ bool usb; /* USB connected */ - bool cable; /* Activ/Passive Cable */ + bool cable; /* Active/Passive Cable */ bool polarity; /* polarity of connected device */ bool hpd_lvl; /* HPD Level assert */ bool hpd_irq; /* HPD IRQ assert */ diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index aaf4479..e3978e2 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -17,7 +17,7 @@ bool help Select this on platforms where the PMC device is discoverable - when scanning busses. + when scanning buses.
config SOC_INTEL_COMMON_BLOCK_PMC_EPOC bool diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig index d4e1c25..bc1eb19 100644 --- a/src/soc/intel/common/block/usb4/Kconfig +++ b/src/soc/intel/common/block/usb4/Kconfig @@ -25,4 +25,4 @@ depends on SOC_INTEL_COMMON_BLOCK_USB4 select PCIEXP_HOTPLUG help - Enable USB4 PCIe resources for reserving hotplug busses and memory. + Enable USB4 PCIe resources for reserving hotplug buses and memory. diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 512f7f5..fdb1028 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -11,7 +11,7 @@ #define MASK_PMC_ACPI_BASE 0xfffc #define PMC_ACPI_CNT 0x44 #define PMC_ACPI_CNT_PWRM_EN (1 << 8) /* PWRM enable */ -#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI eanble */ +#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI enable */ #define PMC_ACPI_CNT_SCIS ((1 << 2) | (1 << 1) | (1 << 0)) /* SCI IRQ select \ */ #define PMC_ACPI_CNT_SCIS_MASK 0x07 diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2d09f51..1a9bfef 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -222,7 +222,7 @@ select COMMONLIB_STORAGE select SDHCI_CONTROLLER help - Read block 0 from each parition of the storage device. User + Read block 0 from each partition of the storage device. User must also enable one or both of COMMONLIB_STORAGE_SD or COMMONLIB_STORAGE_MMC.
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 40e823f..7308712 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -87,7 +87,7 @@ uint8_t DramDensity; uint8_t tCL; /* DRAM CAS Latency in clocks */
- /* ECC scrub interval in miliseconds 1..255 (0 works as feature + /* ECC scrub interval in milliseconds 1..255 (0 works as feature * disable) */ uint8_t EccScrubInterval; diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index c7db8d5..e4015a2 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -55,7 +55,7 @@ //
// -// DEVICE 0 (Memroy Controller Hub) +// DEVICE 0 (Memory Controller Hub) // #define MC_BUS PCI_BUS_NUMBER_QNC #define MC_DEV 0x00 @@ -729,7 +729,7 @@ #define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset #define R_QNC_PCIE_SLCTL 0x58 //~ 59h #define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug intr enable -#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect enable +#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presence detect enable #define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attn Btn Pressed Enable #define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh #define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 8671398..604561a 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -69,7 +69,7 @@ { uint32_t offset;
- /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */ + /* Convert from MTRR index to host bridge offset (Datasheet 12.7.2) */ if (index == MTRR_CAP_MSR) offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; else if (index == MTRR_DEF_TYPE_MSR) diff --git a/src/soc/intel/quark/spi_debug.c b/src/soc/intel/quark/spi_debug.c index b249065..a6b5e69 100644 --- a/src/soc/intel/quark/spi_debug.c +++ b/src/soc/intel/quark/spi_debug.c @@ -79,7 +79,7 @@ printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar);
/* Display the protection ranges */ - printk(BIOS_DEBUG, "BIOS Protected Range Regsiters\n"); + printk(BIOS_DEBUG, "BIOS Protected Range Registers\n"); for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) { status = ctrlr->pbr[index]; printk(BIOS_DEBUG, " %d: 0x%08x: 0x%08x - 0x%08x %s\n", diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 7e06ffa..72c5e47 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -36,7 +36,7 @@ #define CPUID_6_EAX_ISST (1 << 7)
/* - * List of suported C-states in this processor. + * List of supported C-states in this processor. */ enum { C_STATE_C0, /* 0 */ diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 3d12861..dd28255 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -30,7 +30,7 @@ int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels);
/* - * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0 + * Add nau88l25 headset codec on provided SSP link. Return 0 on success, < 0 * on error. */ int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink); diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 9893833..2a71b31 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -511,7 +511,7 @@ TACK, 1, /* [16:16] IOM Acknowledge bit */ DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */ /* display is OFF, clear otherwise */ - Offset(0x70), /* Pyhsical addr is offset 0x70. */ + Offset(0x70), /* Physical addr is offset 0x70. */ IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */ IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */ } diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index ce0b1a6..579ebbc 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -168,7 +168,7 @@ unsigned int num_sockets;
/* - * sort APIC ids in asending order to identify apicid ranges for + * sort APIC ids in ascending order to identify apicid ranges for * each numa domain */ for (dev = all_devices; dev; dev = dev->next) { diff --git a/src/soc/mediatek/common/include/soc/eint_event.h b/src/soc/mediatek/common/include/soc/eint_event.h index 98db7b0..6d544b4 100644 --- a/src/soc/mediatek/common/include/soc/eint_event.h +++ b/src/soc/mediatek/common/include/soc/eint_event.h @@ -6,7 +6,7 @@ #include <device/mmio.h> #include <soc/addressmap.h>
-/* eint event mask cler register */ +/* eint event mask clear register */ struct eint_event_reg { uint32_t eint_event_mask_clr[7]; }; diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index 960d742..340f9ec 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -50,6 +50,6 @@
mtk_soc_disable_l2c_sram();
- /* Reenable MMU with now enlarged L2 cache. Page tables still valid. */ + /* Re-enable MMU with now enlarged L2 cache. Page tables still valid. */ mmu_enable(); } diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 009d03a..8f88509 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -777,7 +777,7 @@ * ISI 0 | 0 * AUD 0 | 1 * XTALK 1 | 0 - * UNKNOW 1 | 1 + * UNKNOWN 1 | 1 */ switch (testaudpat) { case XTALK: diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index f0a9509..e49e222 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -524,7 +524,7 @@ SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, CLK_MISC_CFG_0_METER_DIV, 0); } else { - die("unsupport fmeter type\n"); + die("unsupported fmeter type\n"); }
/* enable frequency meter */ diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index 74dd150..8fd424d 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -844,7 +844,7 @@ SET32_BITFIELDS(&mtk_topckgen->clk_misc_cfg_0, CLK_MISC_CFG_0_METER_DIV, 0); } else { - die("unsupport fmeter type\n"); + die("unsupported fmeter type\n"); }
/* enable frequency meter */ diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h index 0d1fb19..bc033c9 100644 --- a/src/soc/nvidia/tegra124/chip.h +++ b/src/soc/nvidia/tegra124/chip.h @@ -54,7 +54,7 @@ /* Delay before from power on asserting vdd */ int vdd_delay_ms;
- /* Delay beween pwm and backlight_en_gpio is asserted */ + /* Delay between pwm and backlight_en_gpio is asserted */ int pwm_to_bl_delay_ms;
/* Delay before HPD high */ diff --git a/src/soc/nvidia/tegra124/dp.c b/src/soc/nvidia/tegra124/dp.c index 4155c34..5da2c06 100644 --- a/src/soc/nvidia/tegra124/dp.c +++ b/src/soc/nvidia/tegra124/dp.c @@ -465,7 +465,7 @@ return (cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; }
-/* Calcuate if given cfg can meet the mode request. */ +/* Calculate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, const struct soc_nvidia_tegra124_config *config, diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 4fcbaff..0244b47 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -79,7 +79,7 @@ default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE help - Map the UART names to the respective MMIO addres. + Map the UART names to the respective MMIO addresses.
config BOOTROM_SDRAM_INIT bool "SoC BootROM does SDRAM init with full BCT" diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index f76ab34..5846be9 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -137,7 +137,7 @@ tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB))
ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1) - $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") + $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") endif
# BL31 component is placed towards the end of 32-bit address space. This assumes diff --git a/src/soc/nvidia/tegra210/dp.c b/src/soc/nvidia/tegra210/dp.c index 9c55242..a2b06b1 100644 --- a/src/soc/nvidia/tegra210/dp.c +++ b/src/soc/nvidia/tegra210/dp.c @@ -477,7 +477,7 @@ return (link_cfg->lane_count > 0) ? DP_LT_SUCCESS : DP_LT_FAILED; }
-/* Calcuate if given cfg can meet the mode request. */ +/* Calculate if given cfg can meet the mode request. */ /* Return true if mode is possible, false otherwise. */ static int tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp, const struct soc_nvidia_tegra210_config *config, diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index 31ed4f2..bd9a25c 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -94,7 +94,7 @@ /* Return total size of DRAM memory configured on the platform. */ int sdram_size_mb(void);
-/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */ +/* Find memory below and above 4GiB boundary respectively. All units 1MiB. */ void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib); void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib);
diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c index cd1b822..067dc6d 100644 --- a/src/soc/nvidia/tegra210/mipi_dsi.c +++ b/src/soc/nvidia/tegra210/mipi_dsi.c @@ -193,7 +193,7 @@ /* * DCS long write packets contain the word count in the header * bytes 1 and 2 and have a payload containing the DCS command - * byte folowed by word count minus one bytes. + * byte followed by word count minus one bytes. * * DCS short write packets encode the DCS command and up to * one parameter in header bytes 1 and 2. diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index 8ffa0e5..702897f 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -155,7 +155,7 @@
/* * Program CMD mapping. Required before brick mapping, else - * we can't gaurantee CK will be differential at all times. + * we can't guarantee CK will be differential at all times. */ write32(®s->fbio_cfg7, param->EmcFbioCfg7);
@@ -979,7 +979,7 @@
/* Enable EMC pipe clock gating */ write32(®s->cfg_pipe_clk, param->EmcCfgPipeClk); - /* Depending on freqency, enable CMD/CLK fdpd */ + /* Depending on frequency, enable CMD/CLK fdpd */ write32(®s->fdpd_ctrl_cmd_no_ramp, param->EmcFdpdCtrlCmdNoRamp); }
diff --git a/src/soc/qualcomm/ipq40xx/gpio.c b/src/soc/qualcomm/ipq40xx/gpio.c index e7874a7..8e248c5 100644 --- a/src/soc/qualcomm/ipq40xx/gpio.c +++ b/src/soc/qualcomm/ipq40xx/gpio.c @@ -18,7 +18,7 @@ }
/******************************************************* -Function description: configure GPIO functinality +Function description: configure GPIO functionality Arguments : gpio_t gpio - Gpio number unsigned func - Functionality number @@ -77,7 +77,7 @@ }
/******************************************************* -Function description: get GPIO IO functinality details +Function description: get GPIO IO functionality details Arguments : gpio_t gpio - Gpio number unsigned *in - Value of GPIO input diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index da7a6d3..31677e4 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -328,7 +328,7 @@ }
/* - * Function to check wheather Input or Output FIFO + * Function to check whether Input or Output FIFO * has data to be serviced */ static int check_fifo_status(void *reg_addr) @@ -627,7 +627,7 @@ || ((bus == BLSP0_SPI) && (cs > 2)) || ((bus == BLSP1_SPI) && (cs > 0))) { printk(BIOS_ERR, - "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " + "SPI error: unsupported bus %d (Supported buses 0, 1 and 2) " "or chipselect\n", bus); return -1; } diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index e7874a7..8e248c5 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -18,7 +18,7 @@ }
/******************************************************* -Function description: configure GPIO functinality +Function description: configure GPIO functionality Arguments : gpio_t gpio - Gpio number unsigned func - Functionality number @@ -77,7 +77,7 @@ }
/******************************************************* -Function description: get GPIO IO functinality details +Function description: get GPIO IO functionality details Arguments : gpio_t gpio - Gpio number unsigned *in - Value of GPIO input diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index ce420af..cce7ed9 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -84,7 +84,7 @@ qup_config = &gsbi7_qup_config; break; default: - printk(BIOS_ERR, "QUP configuration not defind for GSBI%d.\n", + printk(BIOS_ERR, "QUP configuration not defined for GSBI%d.\n", gsbi_id); return 1; } diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 2b18bda..c538c27 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -758,7 +758,7 @@ || ((bus == GSBI6_SPI) && (cs > 0)) || ((bus == GSBI7_SPI) && (cs > 0))) { printk(BIOS_ERR, "SPI error: unsupported bus %d " - "(Supported busses 0,1 and 2) or chipselect\n", bus); + "(Supported buses 0,1 and 2) or chipselect\n", bus); }
for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 3a3a8bf..15a0998 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -367,7 +367,7 @@ return byte; }
-/* TODO: Implement fuction */ +/* TODO: Implement function */ void uart_fill_lb(void *data) { } diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index 4607dc1..e212b84 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -376,7 +376,7 @@ }
/* - * Function to check wheather Input or Output FIFO + * Function to check whether Input or Output FIFO * has data to be serviced */ static int check_fifo_status(void *reg_addr) diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy.c b/src/soc/qualcomm/sc7180/display/dsi_phy.c index a7b04a8..47f4877 100644 --- a/src/soc/qualcomm/sc7180/display/dsi_phy.c +++ b/src/soc/qualcomm/sc7180/display/dsi_phy.c @@ -23,11 +23,11 @@ #define S_DIV_ROUND_UP(n, d) \ (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
-#define mult_frac(x, numer, denom)( \ +#define mult_frac(x, number, denom)( \ { \ typeof(x) quot = (x) / (denom); \ typeof(x) rem = (x) % (denom); \ - (quot * (numer)) + ((rem * (numer)) / (denom)); \ + (quot * (number)) + ((rem * (number)) / (denom)); \ } \ )
diff --git a/src/soc/samsung/exynos5250/dmc_init_ddr3.c b/src/soc/samsung/exynos5250/dmc_init_ddr3.c index f415020..33725bc 100644 --- a/src/soc/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5250/dmc_init_ddr3.c @@ -124,7 +124,7 @@ if (mem_reset) { /* Send NOP, MRS and ZQINIT commands. * Sending MRS command will reset the DRAM. We should not be - * reseting the DRAM after resume, this will lead to memory + * resetting the DRAM after resume, this will lead to memory * corruption as DRAM content is lost after DRAM reset */ dmc_config_mrs(mem, exynos_dmc); diff --git a/src/soc/samsung/exynos5250/include/soc/gpio.h b/src/soc/samsung/exynos5250/include/soc/gpio.h index 5a58b29..ede70d3 100644 --- a/src/soc/samsung/exynos5250/include/soc/gpio.h +++ b/src/soc/samsung/exynos5250/include/soc/gpio.h @@ -546,7 +546,7 @@ enum mvl3 { LOGIC_0, LOGIC_1, - LOGIC_Z, /* high impedence / tri-stated / floating */ + LOGIC_Z, /* high impedance / tri-stated / floating */ };
#endif /* CPU_SAMSUNG_EXYNOS5250_GPIO_H */ diff --git a/src/soc/samsung/exynos5420/dmc_init_ddr3.c b/src/soc/samsung/exynos5420/dmc_init_ddr3.c index b1eae89..a187f6e 100644 --- a/src/soc/samsung/exynos5420/dmc_init_ddr3.c +++ b/src/soc/samsung/exynos5420/dmc_init_ddr3.c @@ -147,7 +147,7 @@ if (reset) { /* Send NOP, MRS and ZQINIT commands. * Sending MRS command will reset the DRAM. We should not be - * reseting the DRAM after resume, this will lead to memory + * resetting the DRAM after resume, this will lead to memory * corruption as DRAM content is lost after DRAM reset. */ dmc_config_mrs(mem, exynos_drex0); diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h index 14a628d..cc67508 100644 --- a/src/soc/sifive/fu540/ux00ddr.h +++ b/src/soc/sifive/fu540/ux00ddr.h @@ -82,14 +82,14 @@
static inline void ux00ddr_mask_outofrange_interrupts(size_t ahbregaddr) { // Mask off Bit 8, Bit 2 and Bit 1 of Interrupt Status - // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occured - // Bit [1] A memory access outside the defined PHYSICAL memory space has occured + // Bit [2] Multiple accesses outside the defined PHYSICAL memory space have occurred + // Bit [1] A memory access outside the defined PHYSICAL memory space has occurred _REG32(136<<2, ahbregaddr) |= ((1<<OUT_OF_RANGE_OFFSET) | (1<<MULTIPLE_OUT_OF_RANGE_OFFSET)); }
static inline void ux00ddr_mask_port_command_error_interrupt(size_t ahbregaddr) { // Mask off Bit 7 of Interrupt Status - // Bit [7] An error occured on the port command channel + // Bit [7] An error occurred on the port command channel _REG32(136<<2, ahbregaddr) |= (1<<PORT_COMMAND_CHANNEL_ERROR_OFFSET); }
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index 38f2bca..b87b9e4 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -67,7 +67,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 2059db0..88fbf7b 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -77,7 +77,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 88cf47f..9a2c744 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -50,7 +50,7 @@ * The Secondary bus range for PCI0 lets the system * know what bus values are allowed on the downstream * side of this PCI bus if there is a PCI-PCI bridge. - * PCI busses can have 256 secondary busses which + * PCI buses can have 256 secondary buses which * range from [0-0xFF] but they do not need to be * sequential. */ diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 1f14c42..3b07a15 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -162,7 +162,7 @@ if (!res) return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index b4f0c4c..dfebaf0 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -31,7 +31,7 @@ typedef struct southbridge_intel_bd82x6x_config config_t;
/** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 7507cd5..41fc4ee 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -29,7 +29,7 @@ int numcpus = determine_total_number_of_cores(); printk(BIOS_DEBUG, "Found %d CPU(s).\n", numcpus);
- /* without the outer scope, furhter ssdt addition will end up + /* without the outer scope, further ssdt addition will end up * within the processor statement */ acpigen_write_scope("\_SB"); for (cpu=0; cpu < numcpus; cpu++) { diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 988d741..5b9f8be 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -27,7 +27,7 @@ * bit25 (lid_pol): 1=invert lid polarity * bit24 (sm_freeze): 1=freeze idle and standby timers * bit16 (end of smi): 0=disable smi assertion (cleared by hw) - * bits8-15,26: global standby timer inital count 127 * 4minutes + * bits8-15,26: global standby timer initial count 127 * 4minutes * bit2 (thrm_pol): 1=active low THRM# * bit0 (smi_en): 1=disable smi generation upon smi event */ diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 6ff6064..321c605 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -32,7 +32,7 @@ }
/** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index fde06b4..0473de6 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -190,7 +190,7 @@ if (!res) return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)(uintptr_t)base); diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index ff890a2..90d784c 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -183,7 +183,7 @@ if (!res) return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 5efbc9f..885c332 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -183,7 +183,7 @@ if (!res) return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index ef781b7..683715f 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -162,7 +162,7 @@ if (!res) return;
- // NOTE this will break as soon as the Azalia get's a bar above 4G. + // NOTE this will break as soon as the Azalia gets a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 8cc9b42..c14c6a2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -28,7 +28,7 @@ typedef struct southbridge_intel_ibexpeak_config config_t;
/** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index f3c08d8..d0eb4b3 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -25,7 +25,7 @@ #define NMI_OFF 0
/** - * Set miscellanous static southbridge features. + * Set miscellaneous static southbridge features. * * @param dev PCI device with I/O APIC control registers */ diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 82a8f8e..fb4490f 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -187,7 +187,7 @@ break;
default: - printk(BIOS_DEBUG, "Unknown phase: 0x%02x sate: 0x%02x", + printk(BIOS_DEBUG, "Unknown phase: 0x%02x state: 0x%02x", hfs2->progress_code, hfs2->current_state); } printk(BIOS_DEBUG, "\n"); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 598c2dc..7d9fc6d 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -647,7 +647,7 @@ #define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET) #define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET)
-/* Reigsters within the SPIBAR */ +/* Registers within the SPIBAR */ #define SSFC 0x91 #define FDOC 0xb0 #define FDOD 0xb4 diff --git a/src/superio/acpi/pnp_config.asl b/src/superio/acpi/pnp_config.asl index 0257cc7..7ce8fd5 100644 --- a/src/superio/acpi/pnp_config.asl +++ b/src/superio/acpi/pnp_config.asl @@ -26,7 +26,7 @@ Mutex(CONF_MODE_MUTEX, 1)
/* - * Enter configuration mode (and aquire mutex) + * Enter configuration mode (and acquire mutex) * Method must be run before accessing the configuration region. * Parameter is the LDN which should be accessed. Values >= 0xFF mean * no LDN switch should be done. diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 949ec11..38cfe3b 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -103,7 +103,7 @@ /* GPIO Polarity Select: 1: Inverting, 0: Non-inverting */ #define GPIO_REG_POLARITY(x) (0xb0 + (x))
-/* GPIO Inernal Pull-up: 1: Enable, 0: Disable */ +/* GPIO Internal Pull-up: 1: Enable, 0: Disable */ #define GPIO_REG_PULLUP(x) (0xb8 + (x))
/* GPIO Function Select: 1: Simple I/O, 0: Alternate function */ diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 5e23cb0..2061030 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -33,10 +33,10 @@ * NO_W83627HF_GAME: don't expose the game port * NO_W83627HF_MIDI: don't expose the MIDI port * NO_W83627HF_HWMON: don't expose the hardware monitor as - * PnP "Motherboard Ressource" + * PnP "Motherboard Resource" * W83627HF_KBC_COMPAT: show the keyboard controller and the PS/2 mouse as * enabled if it is disabled but an address is assigned - * to it. This may be neccessary in some cases. + * to it. This may be necessary in some cases. * * Datasheet: "W83627HF/F WINBOND I/O" rev. 6.0 * http://www.itox.com/pages/support/wdt/W83627HF.pdf @@ -115,14 +115,14 @@ Offset (0x74), DMA0, 8, /* DMA */ Offset (0xE0), - /* CRE0-CRE4: function logical device dependant, seems to be reserved for ACPI settings */ + /* CRE0-CRE4: function logical device dependent, seems to be reserved for ACPI settings */ CRE0, 8, CRE1, 8, CRE2, 8, CRE3, 8, CRE4, 8, Offset (0xF0), - /* OPT1-OPTA aka CRF0-CRF9: function logical device dependant */ + /* OPT1-OPTA aka CRF0-CRF9: function logical device dependent */ OPT1, 8, OPT2, 8, OPT3, 8, @@ -143,7 +143,7 @@ }) }
- /* Enter configuration mode (and aquire mutex) + /* Enter configuration mode (and acquire mutex) Method must be run before accessing the configuration region. Parameter is the LDN which should be accessed. Values >= 0xFF mean no LDN switch should be done.