[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/alderlake/romstage/fsp_params: fix clock request warning

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83865?usp=email )

Change subject: soc/intel/alderlake/romstage/fsp_params: fix clock request warning
......................................................................

soc/intel/alderlake/romstage/fsp_params: fix clock request warning

If a root port doesn't use a clock request pin, we shouldn't check if
this pin is already used. This fixes the following spurious warning that
was previously printed for each external PCIe port which has the
'PCIE_RP_CLK_REQ_UNUSED' flag set and didn't set 'clk_req' to some
unused clock request pin number:

Found overlapped clkreq assignment on clk req 0

Change-Id: I3ee66ca5ed5a2d06dfb68c45a50e11eb2b93daa0
Signed-off-by: Felix Held 
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 5 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/83865/1

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index d917e6c..a63b64c 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -71,10 +71,12 @@
    		printk(BIOS_WARNING, "Missing root port clock structure definition\n");
    		continue;
    	}
-		if (clk_req_mapping & (1 << cfg[i].clk_req))
-			printk(BIOS_WARNING, "Found overlapped clkreq assignment on clk req %d\n"
-				, cfg[i].clk_req);
+
    	if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
+			if (clk_req_mapping & (1 << cfg[i].clk_req))
+				printk(BIOS_WARNING,
+				       "Found overlapped clkreq assignment on clk req %d\n",
+				       cfg[i].clk_req);
    		m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
    		clk_req_mapping |= 1 << cfg[i].clk_req;
    	}