Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84383?usp=email )
Change subject: soc/amd/glinda/include/soc/smi.h: Update for glinda ......................................................................
soc/amd/glinda/include/soc/smi.h: Update for glinda
It aligns the names in the datasheet with the one in the code. It also removes and adds some.
Resource: Document 57254 Chapter 15.3.5
TODO it may very well be that I don't have the full truth, because most of these register just have a different name and some of these names like ESPI seem more recent that for example LPC.
Change-Id: Iad848ff400ef80777d0cbb2b582b9b5fa8bf11f3 Signed-off-by: Maximilian Brune maximilian.brune@9elements.com --- M src/soc/amd/glinda/include/soc/smi.h 1 file changed, 34 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/84383/1
diff --git a/src/soc/amd/glinda/include/soc/smi.h b/src/soc/amd/glinda/include/soc/smi.h index 3bde93f..850a237 100644 --- a/src/soc/amd/glinda/include/soc/smi.h +++ b/src/soc/amd/glinda/include/soc/smi.h @@ -25,13 +25,13 @@ #define SMITYPE_G_GENINT1_L 0 #define SMITYPE_G_GENINT2_L 1 #define SMITYPE_G_AGPIO3 2 -#define SMITYPE_G_ESPI_ALERT_L 3 +#define SMITYPE_G_LPC_PME_L 3 #define SMITYPE_G_AGPIO4 4 -#define SMITYPE_G_BLINK 5 +#define SMITYPE_G_LPC_PD_L 5 #define SMITYPE_G_SPKR 6 #define SMITYPE_G_AGPIO5 7 #define SMITYPE_G_WAKE_L 8 -#define SMITYPE_G_SPI_TPM_CS_L 9 +#define SMITYPE_G_LPC_SMI_L 9 #define SMITYPE_G_AGPIO6 10 #define SMITYPE_G_AGPIO7 11 #define SMITYPE_G_USBOC0_L 12 @@ -39,7 +39,7 @@ #define SMITYPE_G_USBOC2_L 14 #define SMITYPE_G_USBOC3_L 15 #define SMITYPE_G_AGPIO23 16 -#define SMITYPE_G_AGPIO32 17 +#define SMITYPE_G_ESPI_RESET_L 17 #define SMITYPE_G_FANIN0 18 #define SMITYPE_G_SYSRESET_L 19 #define SMITYPE_G_AGPIO40 20 @@ -49,13 +49,13 @@ #define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \ | (1 << SMITYPE_G_GENINT2_L) \ | (1 << SMITYPE_G_AGPIO3) \ - | (1 << SMITYPE_G_ESPI_ALERT_L) \ + | (1 << SMITYPE_G_LPC_PME_L) \ | (1 << SMITYPE_G_AGPIO4) \ - | (1 << SMITYPE_G_BLINK) \ + | (1 << SMITYPE_G_LPC_PD_L) \ | (1 << SMITYPE_G_SPKR) \ | (1 << SMITYPE_G_AGPIO5) \ | (1 << SMITYPE_G_WAKE_L) \ - | (1 << SMITYPE_G_SPI_TPM_CS_L) \ + | (1 << SMITYPE_G_LPC_SMI_L) \ | (1 << SMITYPE_G_AGPIO6) \ | (1 << SMITYPE_G_AGPIO7) \ | (1 << SMITYPE_G_USBOC0_L) \ @@ -63,7 +63,7 @@ | (1 << SMITYPE_G_USBOC2_L) \ | (1 << SMITYPE_G_USBOC3_L) \ | (1 << SMITYPE_G_AGPIO23) \ - | (1 << SMITYPE_G_AGPIO32) \ + | (1 << SMITYPE_G_ESPI_RESET_L) \ | (1 << SMITYPE_G_FANIN0) \ | (1 << SMITYPE_G_SYSRESET_L) \ | (1 << SMITYPE_G_AGPIO40) \ @@ -72,22 +72,26 @@ | (1 << SMITYPE_G_AGPIO8)) #define SMITYPE_MP2_WAKE 24 #define SMITYPE_MP2_GPIO0 25 -#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_SYS_EVT_B 26 #define SMITYPE_ESPI_WAKE_PME 27 #define SMITYPE_MP2_GPIO1 28 #define SMITYPE_GPP_PME 29 #define SMITYPE_NB_GPP_HOT_PLUG 30 /* 31 Reserved */ -#define SMITYPE_WAKE_L2 32 -#define SMITYPE_PSP 33 -/* 34,35 Reserved */ +#define SMITYPE_WAKE_L 32 +#define SMITYPE_FAKE_0 33 +#define SMITYPE_PSP SMITYPE_FAKE_0 +#define SMITYPE_FAKE_1 34 +#define SMITYPE_FAKE_2 35 #define SMITYPE_ESPI_SCI_B 36 -#define SMITYPE_CIO_FCH_PME_S5_0 37 -#define SMITYPE_CIO_FCH_PME_S5_1 38 -#define SMITYPE_AZPME 39 -#define SMITYPE_GPIO_CTL 41 -#define SMITYPE_XHC2_PME 42 -#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_USB4_0_PME 37 +#define SMITYPE_USB4_1_PME 38 +#define SMITYPE_AZ_WAKE 39 +#define SMITYPE_SCI_40 40 +#define SMITYPE_GPIO_INTR 41 +#define SMITYPE_USBADP_USB3_DRD_0_1 42 +#define SMITYPE_XHC2_PME SMITYPE_USBADP_USB3_DRD_0_1 +#define SMITYPE_ALT_MM_TIMER_ALARM 43 #define SMITYPE_FAN_THERMAL 44 #define SMITYPE_ASF_MASTER_SLAVE 45 #define SMITYPE_I2S_WAKE 46 @@ -98,28 +102,28 @@ #define SMITYPE_PWRBUTTON_UP 51 #define SMITYPE_PROCHOT 52 #define SMITYPE_APU_HW 53 -#define SMITYPE_NB_SCI 54 -#define SMITYPE_RAS_SERR 55 +#define SMITYPE_APU_SCI 54 +#define SMITYPE_INTERNAL_SERR 55 #define SMITYPE_XHC0_PME 56 #define SMITYPE_XHC1_PME 57 #define SMITYPE_ACDC_TIMER 58 -/* 59-60 Reserved */ -#define SMITYPE_XHC3_PME 61 -#define SMITYPE_XHC4_PME 62 +#define SMITYPE_DSM_TRIGGER_0 59 +#define SMITYPE_DSM_TRIGGER_1 60 +#define SMITYPE_USB_XHC3_PME_3 61 +#define SMITYPE_USB_XHC3_PME_4 62 +#define SMITYPE_XHC3_PME SMITYPE_USB_XHC3_PME_3 +#define SMITYPE_XHC4_PME SMITYPE_USB_XHC3_PME_4 #define SMITYPE_CUR_TEMP_STATUS_5 63 #define SMITYPE_KB_RESET 64 #define SMITYPE_SLP_TYP 65 #define SMITYPE_AL2H_ACPI 66 -/* 67 Reserved */ -#define SMITYPE_NB_GPP_PME_PULSE 68 -#define SMITYPE_NB_GPP_HP_PULSE 69 -/* 71 Reserved */ +/* 67-71 Reserved */ #define SMITYPE_GBL_RLS 72 #define SMITYPE_BIOS_RLS 73 #define SMITYPE_PWRBUTTON_DOWN 74 #define SMITYPE_SMI_CMD_PORT 75 #define SMITYPE_USB_SMI 76 -#define SMITYPE_SERIRQ 77 +#define SMITYPE_SERIAL_IRQ 77 #define SMITYPE_SMBUS0_INTR 78 /* 79-80 Reserved */ #define SMITYPE_INTRUDER 81 @@ -135,7 +139,6 @@ #define SMITYPE_SHORT_TIMER 142 #define SMITYPE_LONG_TIMER 143 #define SMITYPE_AB_SMI 144 -#define SMITYPE_ANY_RESET 145 #define SMITYPE_ESPI_SMI 146 /* 147 Reserved */ #define SMITYPE_IOTRAP0 148 @@ -168,7 +171,8 @@ #define SMI_TIMER_EN (1 << 15)
#define SMI_REG_SMITRIG0 0x98 -# define SMITRIG0_PSP (1 << 25) +# define SMITRIG0_FAKESTS0 (1 << 25) +# define SMITRIG0_PSP SMITRIG0_FAKESTS0 # define SMITRG0_EOS (1 << 28) # define SMI_TIMER_SEL (1 << 29) # define SMITRG0_SMIENB (1 << 31)