yuchi.chen@intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83319?usp=email )
Change subject: add PCIe SRIOV definitions ......................................................................
add PCIe SRIOV definitions
Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013 Signed-off-by: Yuchi Chen yuchi.chen@intel.com --- M src/include/device/pci_def.h 1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83319/1
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 6d61e6d..e372627 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -478,6 +478,7 @@ #define PCIE_EXT_CAP_LTR_ID 0x0018 #define PCIE_EXT_CAP_RESIZABLE_BAR 0x0015 #define PCIE_EXT_CAP_RCECEA_ID 0x0007 +#define PCIE_EXT_CAP_SRIOV_ID 0x0010
/* Secondary PCI Express Extended Capability Structure */ #define PCI_EXP_SEC_CAP_ID 0x19 @@ -579,6 +580,13 @@ #define PCI_RCECEA_BITMAP 4 #define PCI_RCECEA_BUSNUM 8
+/* Single Root IO Virtualization */ +#define PCIE_EXT_CAP_SRIOV_TOTAL_VFS 0x0e +#define PCIE_EXT_CAP_SRIOV_SUPPORTED_PAGE_SIZE 0x1c +#define PCIE_EXT_CAP_SRIOV_SYSTEM_PAGE_SIZE 0x20 +#define PCIE_EXT_CAP_SRIOV_VF_BAR0 0x24 +#define PCIE_EXT_CAP_SRIOV_VF_BAR5 0x38 + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded