[coreboot-gerrit] Change in coreboot[master]: mb/adlrvp_m: Add hook function to return status EC in RW status

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58090 )

Change subject: mb/adlrvp_m: Add hook function to return status EC in RW status
......................................................................

mb/adlrvp_m: Add hook function to return status EC in RW status

function uses GPIO EC7 to signal if EC is in RW (un trusted) or RO Y(trusted)

Signed-off-by: Anil Kumar K  
Change-Id: I07fdd0dd9a42956f386604184d894425329db592
---
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/adlrvp/gpio_m.c
M src/mainboard/intel/adlrvp/include/baseboard/gpio.h
3 files changed, 13 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/58090/1

diff --git a/src/mainboard/intel/adlrvp/chromeos.c b/src/mainboard/intel/adlrvp/chromeos.c
index d963c73..f5c7ffe 100644
--- a/src/mainboard/intel/adlrvp/chromeos.c
+++ b/src/mainboard/intel/adlrvp/chromeos.c
@@ -12,7 +12,7 @@
    	{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
    	{-1, ACTIVE_HIGH, 0, "power"},
    	{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-		{-1, ACTIVE_HIGH, 0, "EC in RW"},
+		{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
    };
    lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
@@ -44,3 +44,10 @@
    gpios = variant_cros_gpios(&num);
    chromeos_acpi_gpio_generate(gpios, num);
 }
+
+int get_ec_is_trusted(void)
+{
+	/* EC is trusted if not in RW. */
+	return !gpio_get(GPIO_EC_IN_RW);
+}
+
diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c
index 6f0568d..2026fc5 100644
--- a/src/mainboard/intel/adlrvp/gpio_m.c
+++ b/src/mainboard/intel/adlrvp/gpio_m.c
@@ -89,6 +89,9 @@
    PAD_CFG_GPO(GPP_D15, 1, PLTRST),
    /* D9  : WWAN_FCP_POWER_OFF_N */
    PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+	
+	/* EC_IN_RW */
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),

/* H0  : PCH_SSD_RST# */
    PAD_CFG_GPO(GPP_H0, 1, PLTRST),
diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
index de0adf6..c6d1217 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h
@@ -12,4 +12,6 @@
 /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
 #define GPE_EC_WAKE	GPE0_LAN_WAK

+#define GPIO_EC_IN_RW   GPP_E7
+
 #endif /* __BASEBOARD_GPIO_H__ */