Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60170 )
Change subject: Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com ......................................................................
Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com
src/soc/intel/alderlake/meminit.c : Changes adopted as per new FSP DQS & UPD calls.
Meminit function call in coreboot has been updated as per new FSP UPD and DQS in headers.
change-Id: I0c6ae72610da39fc18ff252c440d006e83c570c1 --- M src/soc/intel/alderlake/meminit.c 1 file changed, 26 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/60170/1
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 44071db..d81e856 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -123,14 +123,14 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) { uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { - [0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, }, - [1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, }, - [2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, }, - [3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, }, - [4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, }, - [5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, }, - [6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, }, - [7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, }, + [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, + [1] = { &mem_cfg->MemorySpdPtr002, &mem_cfg->MemorySpdPtr003, }, + [2] = { &mem_cfg->MemorySpdPtr004, &mem_cfg->MemorySpdPtr005, }, + [3] = { &mem_cfg->MemorySpdPtr006, &mem_cfg->MemorySpdPtr007, }, + [4] = { &mem_cfg->MemorySpdPtr008, &mem_cfg->MemorySpdPtr009, }, + [5] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, }, + [6] = { &mem_cfg->MemorySpdPtr012, &mem_cfg->MemorySpdPtr013, }, + [7] = { &mem_cfg->MemorySpdPtr014, &mem_cfg->MemorySpdPtr015, }, }; uint8_t *disable_channel_upds[MRC_CHANNELS] = { &mem_cfg->DisableMc0Ch0, @@ -179,17 +179,17 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dq_upds[MRC_CHANNELS] = { - &mem_cfg->DqMapCpu2DramCh0, - &mem_cfg->DqMapCpu2DramCh1, - &mem_cfg->DqMapCpu2DramCh2, - &mem_cfg->DqMapCpu2DramCh3, - &mem_cfg->DqMapCpu2DramCh4, - &mem_cfg->DqMapCpu2DramCh5, - &mem_cfg->DqMapCpu2DramCh6, - &mem_cfg->DqMapCpu2DramCh7, + &mem_cfg->DqMapCpu2DramMc0Ch0, + &mem_cfg->DqMapCpu2DramMc0Ch1, + &mem_cfg->DqMapCpu2DramMc0Ch2, + &mem_cfg->DqMapCpu2DramMc0Ch3, + &mem_cfg->DqMapCpu2DramMc0Ch4, + &mem_cfg->DqMapCpu2DramMc0Ch5, + &mem_cfg->DqMapCpu2DramMc0Ch6, + &mem_cfg->DqMapCpu2DramMc0Ch7, };
- const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0);
_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!");
@@ -200,17 +200,17 @@ const struct mb_cfg *mb_cfg, bool auto_detect) { void *dqs_upds[MRC_CHANNELS] = { - &mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1, - &mem_cfg->DqsMapCpu2DramCh2, - &mem_cfg->DqsMapCpu2DramCh3, - &mem_cfg->DqsMapCpu2DramCh4, - &mem_cfg->DqsMapCpu2DramCh5, - &mem_cfg->DqsMapCpu2DramCh6, - &mem_cfg->DqsMapCpu2DramCh7, + &mem_cfg->DqsMapCpu2DramMc0Ch0, + &mem_cfg->DqsMapCpu2DramMc0Ch1, + &mem_cfg->DqsMapCpu2DramMc0Ch2, + &mem_cfg->DqsMapCpu2DramMc0Ch3, + &mem_cfg->DqsMapCpu2DramMc0Ch4, + &mem_cfg->DqsMapCpu2DramMc0Ch5, + &mem_cfg->DqsMapCpu2Drammc0Ch6, + &mem_cfg->DqsMapCpu2DramMc0Ch7, };
- const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0); + const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0);
_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!");