Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84278?usp=email )
Change subject: mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPU ......................................................................
mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPU
Check that lnkCap supports ASPM L1, so set it to ASPM_L1 to avoid excessive power consumption.
BUG=b:363854853 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I386f8e88a5af661b1f4c04d2e2a34cd181608bd8 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/84278 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subratabanik@google.com Reviewed-by: srinivas.kulkarni@intel.com --- M src/mainboard/google/brox/variants/brox/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: Subrata Banik: Looks good to me, approved srinivas.kulkarni@intel.com: Looks good to me, but someone else must approve build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index f2342f0..79771eb 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -273,6 +273,7 @@ .clk_req = 3, .clk_src = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1 }" probe STORAGE STORAGE_NVME probe unprovisioned