Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57747 )
Change subject: amdfwtool: Add ISH header support for A/B recovery layout ......................................................................
Patch Set 32:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/57747/comment/ef6a5b9f_6e38a48a PS24, Line 11: EFS -> PSP L1 0x48 -> PSP L2 A -> ISH A -> BIOS L2 A
shouldn't this be: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A ? same for the line below
Done
File util/amdfwtool/amdfwtool.h:
https://review.coreboot.org/c/coreboot/+/57747/comment/83cce90b_93cdacf4 PS24, Line 217: uint32_t glitch_retry_count;
document #55758 Rev. 1.13 has one byte for this and 3 reserved bytes after that. […]
Done
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/57747/comment/1e8b2908_b2824c82 PS24, Line 394: 0x1000
would be good to have a define for this
Done
https://review.coreboot.org/c/coreboot/+/57747/comment/77e9e28a_e784c164 PS24, Line 396: 0x1000
from the documentation i'd say that this value is correct; I think all modern spi flash chips have a […]
Done
https://review.coreboot.org/c/coreboot/+/57747/comment/5da641cc_bc59d75c PS24, Line 670: 0x2
the specification i'm looking says that this should be 1
Not in spec, people said as long as the update_retry_count in A is higher than B
https://review.coreboot.org/c/coreboot/+/57747/comment/d8ddc664_79cc2a44 PS24, Line 671: 0xf
the specification i'm looking says that this should be 1
Not sure. Copied from CRB.
https://review.coreboot.org/c/coreboot/+/57747/comment/f6b70a82_a0bb1ed9 PS24, Line 686: 0x1000
would be good to have a define for this
Done