Alexander Couzens (lynxis@fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9250
-gerrit
commit 4116761c8231372b1eebc1f990c630766ba11783 Author: Alexander Couzens lynxis@fe80.eu Date: Thu Apr 2 23:12:50 2015 +0200
device_t: remove all reference of device_t in SMM, PRE_RAM, ROM_CC
device_t is a type which should only used in RAM stage. This also removes a x86 workaround which defined it to a dev_pcifn_t compatible type.
Change-Id: Ied65fdab548d2477c284642663fd72c530608cd2 Signed-off-by: Alexander Couzens lynxis@fe80.eu --- src/arch/x86/include/arch/io.h | 4 ---- src/include/device/device.h | 2 +- src/include/device/pci.h | 6 +++--- src/northbridge/intel/nehalem/acpi.c | 2 +- src/southbridge/intel/bd82x6x/early_usb.c | 4 ++-- src/southbridge/intel/bd82x6x/pch.c | 6 ++++-- src/southbridge/intel/ibexpeak/early_smbus.c | 2 +- src/southbridge/intel/ibexpeak/early_thermal.c | 2 +- src/southbridge/intel/ibexpeak/pch.h | 1 + src/southbridge/intel/ibexpeak/smi.c | 4 ++-- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- 11 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 3130f64..bba58dd 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -222,10 +222,6 @@ static inline int log2f(int value)
#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
-/* FIXME: Sources for romstage still use device_t. */ -/* Use pci_devfn_t or pnp_devfn_t instead */ -typedef u32 device_t; - /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access diff --git a/src/include/device/device.h b/src/include/device/device.h index c1c9fdb..af3d52e 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -15,9 +15,9 @@ #include <device/path.h>
struct device; +typedef struct device * device_t;
#ifndef __SIMPLE_DEVICE__ -typedef struct device * device_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations; diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 4e712f9..174f1a7 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -103,13 +103,13 @@ static inline const struct pci_operations *ops_pci(device_t dev)
#endif /* ! __SIMPLE_DEVICE__ */
-#ifdef __PRE_RAM__ +#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__) unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); -#else /* !__PRE_RAM__ */ +#else /* !__PRE_RAM__ && !__SMM__ && !__ROMCC__ */ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); -#endif /* __PRE_RAM__ */ +#endif /* __PRE_RAM__ || __SMM__ || __ROMCC__ */
void pci_early_bridge_init(void); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 4a208ce..73554a4 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -135,7 +135,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion) /* Initialize IGD OpRegion, called from ACPI code */ int init_igd_opregion(igd_opregion_t * opregion) { - device_t igd; + pci_devfn_t igd; u16 reg16;
memset((void *)opregion, 0, sizeof(igd_opregion_t)); diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index ea2bf38..fd24b41 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -36,8 +36,8 @@ */ void enable_usb_bar(void) { - device_t usb0 = PCH_EHCI1_DEV; - device_t usb1 = PCH_EHCI2_DEV; + pci_devfn_t usb0 = PCH_EHCI1_DEV; + pci_devfn_t usb1 = PCH_EHCI2_DEV; u32 cmd;
/* USB Controller 1 */ diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 37a0b64..f80f859 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -35,11 +35,12 @@ static int pch_type = -1;
int pch_silicon_revision(void) { - device_t dev;
#ifdef __SMM__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif
@@ -50,11 +51,12 @@ int pch_silicon_revision(void)
int pch_silicon_type(void) { - device_t dev;
#ifdef __SMM__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index cf02b9e..7a57d7e 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -27,7 +27,7 @@
void enable_smbus(void) { - device_t dev; + pci_devfn_t dev;
/* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index e765943..8acfc91 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -27,7 +27,7 @@ which is done at the end of raminit. */ void early_thermal_init(void) { - device_t dev; + pci_devfn_t dev; msr_t msr;
dev = PCI_DEV(0x0, 0x1f, 0x6); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 12e9345..67955eb 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -65,6 +65,7 @@ void intel_pch_finalize_smm(void); #if !defined(__PRE_RAM__) #if !defined(__SMM__) #include "chip.h" +#include <device/device.h> void pch_enable(device_t dev); #endif int pch_silicon_revision(void); diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2ce9072..8797f09 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -327,8 +327,8 @@ static int smm_handler_copied = 0;
static void smm_install(void) { - device_t dev = PCI_DEV(0, 0, 0); - device_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1); + pci_devfn_t dev = PCI_DEV(0, 0, 0); + pci_devfn_t qpdev = PCI_DEV(QUICKPATH_BUS, 0, 1); u32 smm_base = 0xa0000; struct ied_header ied = { .signature = "INTEL RSVD", diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 019e6db..4081dae 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -264,7 +264,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID);