[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 funcions

[Cliff Huang (Code Review)]

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 funcions
......................................................................

soc/intel/common/block/pmc: Add GPE1 funcions

- Requires CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag.
- The existing static gpe functions has been renamed with ppe0.
- Add gpe1 functions.

BUG=362310295
TEST=Build with CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPE1 flag, boot DUT,
and check if GPE1 sts bits have been printed during boot.

Signed-off-by: Cliff Huang 
Change-Id: I7ac1fbe6d45cbe0c86c3f72911900d92a186168d
---
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
2 files changed, 55 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/84104/1

diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index fd61489..b77d236 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -214,6 +214,16 @@
  */
 const char *const *soc_std_gpe_sts_array(size_t *a);

+
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1)
+/*
+ * This function returns array of string which represents
+ * names for the STD GPE1 status register bits.
+ * Size of the array is returned as an output parameter.
+ */
+const char *const *soc_std_gpe1_sts_array(int idx, size_t *a);
+#endif
+
 /*
  * This function gets the gpe0 dwX values from devicetree
  * for pmc_gpe_init which will use those to set the GPE_CFG
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 7650fe4..7da62a8 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -320,7 +320,7 @@
 }

/* Clear the gpio gpe0 status bits in ACPI registers */
-static void pmc_clear_gpi_gpe_status(void)
+static void pmc_clear_gpi_gpe0_status(void)
 {
    int i;

@@ -333,14 +333,14 @@
    }
 }

-static uint32_t reset_std_gpe_status(void)
+static uint32_t reset_std_gpe0_status(void)
 {
    uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
    outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD));
    return gpe_sts;
 }

-static uint32_t print_std_gpe_sts(uint32_t gpe_sts)
+static uint32_t print_std_gpe0_sts(uint32_t gpe_sts)
 {
    size_t array_size;
    const char *const *sts_arr;
@@ -357,15 +357,53 @@
    return gpe_sts;
 }

-static void pmc_clear_std_gpe_status(void)
+static void pmc_clear_std_gpe0_status(void)
 {
-	print_std_gpe_sts(reset_std_gpe_status());
+	print_std_gpe0_sts(reset_std_gpe0_status());
 }

+
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1)
+/* Clear the gpio gpe1 status bits in ACPI registers */
+static void pmc_clear_gpi_gpe1_status(void)
+{
+	int i;
+
+	for (i = 0; i < GPE1_REG_MAX; i++) {
+		uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE1_STS(i));
+		outl(gpe_sts, ACPI_BASE_ADDRESS + GPE1_STS(i));
+	}
+}
+
+static void print_std_gpe1_sts(void)
+{
+	size_t array_size;
+	const char *const *sts_arr;
+	int i;
+
+	for (i = 0; i < GPE1_REG_MAX; i++) {
+		uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE1_STS(i));
+		sts_arr = soc_std_gpe1_sts_array(i, &array_size);
+		printk(BIOS_DEBUG, "GPE1 STD STS[%d]: ", i);
+		print_num_status_bits(array_size, gpe_sts, sts_arr);
+	}
+	printk(BIOS_DEBUG, "\n");
+}
+
+static void pmc_clear_std_gpe1_status(void)
+{
+	print_std_gpe1_sts();
+	pmc_clear_gpi_gpe1_status();
+}
+#endif
+
 void pmc_clear_all_gpe_status(void)
 {
-	pmc_clear_std_gpe_status();
-	pmc_clear_gpi_gpe_status();
+	pmc_clear_std_gpe0_status();
+#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1)
+	pmc_clear_std_gpe1_status();
+#endif
+	pmc_clear_gpi_gpe0_status();
 }

__weak