[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure Type-C IOM base address and size

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41759 )

Change subject: soc/intel/tigerlake: Configure Type-C IOM base address and size
......................................................................

soc/intel/tigerlake: Configure Type-C IOM base address and size

This adds Type-C IO Manageability engine base address and size. IOM
register base is in offset 0x7110 from MCHBAR and its port ID is 0xc1.
IOM has base address 0xfbc10000 with size 0x1600.

BUG=:b:156016218
TEST=Built and booted on Volteer.

Signed-off-by: John Zhao 
Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907
---
M src/soc/intel/tigerlake/include/soc/iomap.h
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/41759/1

diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h
index 282092f..cd964f0 100644
--- a/src/soc/intel/tigerlake/include/soc/iomap.h
+++ b/src/soc/intel/tigerlake/include/soc/iomap.h
@@ -84,6 +84,8 @@
 #define EARLY_I2C_BASE_ADDRESS	0xfe020000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x2000 * (x)))

+#define IOM_BASE_ADDRESS	0xfbc10000
+#define IOM_BASE_SIZE		0x1600

/*
  * I/O port address space