[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48079 )

Change subject: mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU
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Patch Set 2: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/48079/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/48079/2//COMMIT_MSG@10 
PS2, Line 10: 1. tCKAVGmax
            : 2. CAS Latencies supported (First Byte)
            : 3. CAS Latencies supported (Second Byte)
            : 4. CAS Latencies supported (Third Byte)
            : 5. Minimum CAS Latency (tAAmin)
            : 6. Read and Write Latency Set options
            : 7. FTB for tAAmin
            : 8. FTB for tCKAVGmax
            : 9. FTB for tCKAVGmin
Instead of listing the low-level changes, how about explaining the high-level changes? For example:

1. Raise/Lower tCKAVGmax from X ns to Y ns