[coreboot-gerrit] [XS] Change in coreboot[main]: soc/mediatek/mt8195: Fix SCP register address

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85436?usp=email )

Change subject: soc/mediatek/mt8195: Fix SCP register address
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soc/mediatek/mt8195: Fix SCP register address

The parentheses are missing in the mtk_scp macro definition.

The only usage is

SET32_BITFIELDS(&mtk_scp->scp_clk_on_ctrl,
                 SCP_CLK_ON_CTRL, 1);

I guess that bit is already set by default, so there's no ULPOSC clock
issue found so far.

BUG=none
TEST=none
BRANCH=cherry

Change-Id: I2dbb5c465ee60f0c4dce8ff77b8d3a39db42e4f5
Signed-off-by: Yu-Ping Wu 
---
M src/soc/mediatek/mt8195/include/soc/pmif.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85436/1

diff --git a/src/soc/mediatek/mt8195/include/soc/pmif.h b/src/soc/mediatek/mt8195/include/soc/pmif.h
index cec23d7..530b31e 100644
--- a/src/soc/mediatek/mt8195/include/soc/pmif.h
+++ b/src/soc/mediatek/mt8195/include/soc/pmif.h
@@ -134,7 +134,7 @@

check_member(mtk_scp_regs, scp_clk_on_ctrl, 0x6C);

-#define mtk_scp		((struct mtk_scp_regs *)SCP_CFG_BASE + 0x21000)
+#define mtk_scp		((struct mtk_scp_regs *)(SCP_CFG_BASE + 0x21000))

enum {
    PMIF_TARGET_FREQ_MHZ = 248,