Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69870?usp=email )
(
5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B ......................................................................
intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference.
Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I11241836ecc9066d323977b030686567c87ed256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Sean Rhodes sean@starlabs.systems Reviewed-by: Krystian Hebel krystian.hebel@3mdeb.com --- M src/soc/intel/common/block/smm/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: Krystian Hebel: Looks good to me, approved build bot (Jenkins): Verified Sean Rhodes: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index 2d960d6..4944ade 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -44,3 +44,12 @@ help HECI disable using SMM. Select this option to make HECI disable using SMM mode, independent of dedicated UPD to perform HECI disable. + +config PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + Intel Core processors select the periodic SMI rate via GEN_PMCON_A. + On Intel Atom processors the register is different and they use + GEN_PMCON_B/GEN_PMCON2 with different address.