[coreboot-gerrit] Change in coreboot[master]: test/lib: Add non-existent DIMMs test case in spd_cache-test

[Eric Lai (Code Review)]

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63642 )

Change subject: test/lib: Add non-existent DIMMs test case in spd_cache-test
......................................................................

test/lib: Add non-existent DIMMs test case in spd_cache-test

Add non-existent DIMMs test case in spd_cache-test.

BUG=b:213964936
TEST=test passed

Signed-off-by: Eric Lai 
Change-Id: I19b5ff7fb210b68a4ada18d8387de4ebcd054145
---
M tests/lib/spd_cache-test.c
1 file changed, 21 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/63642/1

diff --git a/tests/lib/spd_cache-test.c b/tests/lib/spd_cache-test.c
index 48f06e3..c1a6113 100644
--- a/tests/lib/spd_cache-test.c
+++ b/tests/lib/spd_cache-test.c
@@ -11,6 +11,13 @@
 struct region_device flash_rdev_rw;
 static char *flash_buffer = NULL;
 static size_t flash_buffer_size = 0;
+static u8 valid_addr_map[][4] = {
+	{0x50, 0x51, 0x52, 0x53},
+	{0x50, 0, 0x52, 0},
+	{0, 0x51, 0, 0x53},
+	{0x50, 0, 0, 0},
+	{0, 0, 0x52, 0},
+	};

static int setup_spd_cache(void **state)
 {
@@ -38,6 +45,7 @@
    free(flash_buffer);
    flash_buffer = NULL;
    flash_buffer_size = 0;
+	valid_addr_map = {0};
    return 0;
 }

@@ -216,18 +224,21 @@
 {
    uint8_t *spd_cache;
    size_t spd_cache_sz;
-	struct spd_block blk = {.addr_map = {0x50, 0x51, 0x52, 0x53},
-				.spd_array = {0}, .len = 0};
+	struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0};

-	assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz));
-	fill_spd_cache_ddr4(spd_cache, spd_cache_sz);
-	assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk));
-	get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn);
-	*(u32 *)(spd_cache + SC_SPD_OFFSET(0) + DDR4_SPD_SN_OFF) = 0x43211234;
+	for (uint8_t i = 0; i < arraysize(valid_addr_map); i++) {
+		blk.addr_map = valid_addr_map[i];
+		assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz));
+		fill_spd_cache_ddr4(spd_cache, spd_cache_sz);
+		assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk));
+		get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn);
+		*(u32 *)(spd_cache + SC_SPD_OFFSET(0) + DDR4_SPD_SN_OFF) = 0x43211234;

-	get_spd_sn_ret_sn_idx = 0;
-	will_return_always(get_spd_sn, CB_SUCCESS);
-	assert_true(check_if_dimm_changed(spd_cache, &blk));
+		get_spd_sn_ret_sn_idx = 0;
+		will_return_always(get_spd_sn, CB_SUCCESS);
+		assert_true(check_if_dimm_changed(spd_cache, &blk));
+		memset(spd_cache, 0, spd_cache_sz);
+	}
 }

int main(void)