[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add UPDs for support edp phy tuning adjust

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48733

to review the following change.

Change subject: soc/amd/picasso: Add UPDs for support edp phy tuning adjust
......................................................................

soc/amd/picasso: Add UPDs for support edp phy tuning adjust

Add UPDs for edp phy tuning adjust.

BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang 
Change-Id: I389bc4b5726f70bb1edfd858dba1c575cf68050b
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 41 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/48733/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index c0a6457..2e6f8d4 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -57,6 +57,18 @@
    SD_EMMC_DRIVE_STRENGTH_D,
 };

+/// dpphy_override
+enum sysinfo_dpphy_override {
+	ENABLE_DVI_TUNINGSET   = 0x01,
+	ENABLE_HDMI_TUNINGSET  = 0x02,
+	ENABLE_HDMI6G_TUNINGSET  = 0x04,
+	ENABLE_DP_TUNINGSET  = 0x08,
+	ENABLE_DP_HBR3_TUNINGSET  = 0x10,
+	ENABLE_DP_HBR_TUNINGSET  = 0x20,
+	ENABLE_DP_HBR2_TUNINGSET  = 0x40,
+	ENABLE_EDP_TUNINGSET  = 0x80,
+};
+
 struct soc_amd_picasso_config {
    struct soc_amd_common_config common_config;
    /*
@@ -219,6 +231,19 @@

/* The array index is the general purpose PCIe clock output number. */
    enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
+
+	/* eDP phy tuning settings */
+	uint8_t   dp_phy_override;
+	uint16_t  edp_phy_sel;
+	uint8_t   edp_version;
+	uint16_t  edp_table_size;
+
+	struct {
+		uint8_t   dp_vs_pemph_level;
+		uint8_t   deemph_6db4;
+		uint8_t   boostadj;
+		uint16_t  margin_deemph;
+	} edp_tuningset;
 };

#endif /* __PICASSO_CHIP_H__ */
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index c7befe4..86b3eba 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -142,6 +142,21 @@
    scfg->fch_ioapic_id = CONFIG_PICASSO_FCH_IOAPIC_ID;
 }

+static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg,
+			const struct soc_amd_picasso_config *cfg)
+{
+	if (cfg->dp_phy_override) {
+		scfg->DpPhyOverride = cfg->dp_phy_override;
+		scfg->EDpPhySel = cfg->edp_phy_sel;
+		scfg->EDpVersion = cfg->edp_version;
+		scfg->EDpTableSize = cfg->edp_table_size;
+		scfg->DpVsPemphLevel = cfg->edp_tuningset.dp_vs_pemph_level;
+		scfg->MarginDeemPh = cfg->edp_tuningset.margin_deemph;
+		scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4;
+		scfg->BoostAdj = cfg->edp_tuningset.boostadj;
+	}
+}
+
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
    const struct soc_amd_picasso_config *cfg;
@@ -152,4 +167,5 @@
    fsp_fill_pcie_ddi_descriptors(scfg);
    fsp_assign_ioapic_upds(scfg);
    fsp_usb_oem_customization(scfg, cfg);
+	fsp_edp_tuning_upds(scfg, cfg);
 }