Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80355?usp=email )
Change subject: soc/amd: drop unneeded data_fabric_set_mmio_np ......................................................................
soc/amd: drop unneeded data_fabric_set_mmio_np
Drop the unneeded data_fabric_set_mmio_np function and the corresponding SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION Kconfig symbol. In systems with only one FCH, its MMIO region will be subtractively decoded and there's no need to add a non-posted data fabric MMIO region after the FSP/openSIL has already configured the data fabric decode windows. In systems with more than one FCH, openSIL will already take care of initializing everything for the additional FCH, so we also won't need to do anything in that case. Since dropping this function also removes both data_fabric_print_mmio_conf calls before and after adding the unneeded non-posted MMIO region, replace the data_fabric_set_mmio_np call with a data_fabric_print_mmio_conf call to still print the data fabric MMIO decode regions set up by the FSP/openSIL.
TEST=Mandolin still boots successfully
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I474b6e066060abb3fe5b78505521c7782cc192ee --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/chip.c M src/soc/amd/common/block/data_fabric/Kconfig M src/soc/amd/common/block/data_fabric/Makefile.mk D src/soc/amd/common/block/data_fabric/np_region.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/chip.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/chip.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/chip.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/chip.c 14 files changed, 6 insertions(+), 139 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/80355/1
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 0ef658c..4e22005 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -43,7 +43,6 @@ select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 7d315cb..83fd5c6 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -41,7 +41,7 @@
amd_fsp_silicon_init();
- data_fabric_set_mmio_np(); + data_fabric_print_mmio_conf();
fch_init(chip_info); } diff --git a/src/soc/amd/common/block/data_fabric/Kconfig b/src/soc/amd/common/block/data_fabric/Kconfig index da35dae..add2374 100644 --- a/src/soc/amd/common/block/data_fabric/Kconfig +++ b/src/soc/amd/common/block/data_fabric/Kconfig @@ -4,14 +4,6 @@ Select this option to add data fabric configuration related functionality to the build.
-config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION - bool - depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC - help - Select this option to include the code to make sure that there's a - non-posted MMIO region configured in the data fabric registers that - covers the FCH MMIO from the HPET up to right below the LAPIC. - config SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN bool depends on SOC_AMD_COMMON_BLOCK_DATA_FABRIC diff --git a/src/soc/amd/common/block/data_fabric/Makefile.mk b/src/soc/amd/common/block/data_fabric/Makefile.mk index b0684f4..55a4d3f 100644 --- a/src/soc/amd/common/block/data_fabric/Makefile.mk +++ b/src/soc/amd/common/block/data_fabric/Makefile.mk @@ -2,7 +2,6 @@
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC) += data_fabric_helper.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += domain.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION) += np_region.c
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT),y) ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN) += pci_segment_multi.c diff --git a/src/soc/amd/common/block/data_fabric/np_region.c b/src/soc/amd/common/block/data_fabric/np_region.c deleted file mode 100644 index dd82e5e..0000000 --- a/src/soc/amd/common/block/data_fabric/np_region.c +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/data_fabric.h> -#include <arch/hpet.h> -#include <console/console.h> -#include <cpu/x86/lapic_def.h> -#include <soc/data_fabric.h> -#include <types.h> - -static void data_fabric_disable_mmio_reg(unsigned int reg) -{ - union df_mmio_control ctrl = { .dst_fabric_id = IOMS0_FABRIC_ID }; - data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw); - data_fabric_broadcast_write32(DF_MMIO_BASE(reg), 0); - data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), 0); -} - -static bool is_mmio_reg_disabled(unsigned int reg) -{ - union df_mmio_control ctrl; - ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(reg)); - return !(ctrl.we || ctrl.re); -} - -static int data_fabric_find_unused_mmio_reg(void) -{ - for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { - if (is_mmio_reg_disabled(i)) - return i; - } - return -1; -} - -void data_fabric_set_mmio_np(void) -{ - /* - * Mark region from HPET-LAPIC or 0xfed00000-0xfee00000-1 as NP. - * - * AGESA has already programmed the NB MMIO routing, however nothing - * is yet marked as non-posted. - * - * If there exists an overlapping routing base/limit pair, trim its - * base or limit to avoid the new NP region. If any pair exists - * completely within HPET-LAPIC range, remove it. If any pair surrounds - * HPET-LAPIC, it must be split into two regions. - * - * TODO(b/156296146): Remove the settings from AGESA and allow coreboot - * to own everything. If not practical, consider erasing all settings - * and have coreboot reprogram them. At that time, make the source - * below more flexible. - * * Note that the code relies on the granularity of the HPET and - * LAPIC addresses being sufficiently large that the shifted limits - * +/-1 are always equivalent to the non-shifted values +/-1. - */ - - unsigned int i; - int reg; - uint32_t base, limit; - union df_mmio_control ctrl; - const uint32_t np_bot = HPET_BASE_ADDRESS >> DF_MMIO_SHIFT; - const uint32_t np_top = (LAPIC_DEFAULT_BASE - 1) >> DF_MMIO_SHIFT; - - data_fabric_print_mmio_conf(); - - for (i = 0; i < DF_MMIO_REG_SET_COUNT; i++) { - /* Adjust all registers that overlap */ - ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i)); - if (!(ctrl.we || ctrl.re)) - continue; /* not enabled */ - - base = data_fabric_broadcast_read32(DF_MMIO_BASE(i)); - limit = data_fabric_broadcast_read32(DF_MMIO_LIMIT(i)); - - if (base > np_top || limit < np_bot) - continue; /* no overlap at all */ - - if (base >= np_bot && limit <= np_top) { - data_fabric_disable_mmio_reg(i); /* 100% within, so remove */ - continue; - } - - if (base < np_bot && limit > np_top) { - /* Split the configured region */ - data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1); - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - /* Although a pair could be freed later, this condition is - * very unusual and deserves analysis. Flag an error and - * leave the topmost part unconfigured. */ - printk(BIOS_ERR, "Not enough NB MMIO routing registers\n"); - continue; - } - data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_top + 1); - data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), limit); - data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), ctrl.raw); - continue; - } - - /* If still here, adjust only the base or limit */ - if (base <= np_bot) - data_fabric_broadcast_write32(DF_MMIO_LIMIT(i), np_bot - 1); - else - data_fabric_broadcast_write32(DF_MMIO_BASE(i), np_top + 1); - } - - reg = data_fabric_find_unused_mmio_reg(); - if (reg < 0) { - printk(BIOS_ERR, "cannot configure region as NP\n"); - return; - } - - union df_mmio_control np_ctrl = { .dst_fabric_id = IOMS0_FABRIC_ID, - .np = 1, .we = 1, .re = 1 }; - data_fabric_broadcast_write32(DF_MMIO_BASE(reg), np_bot); - data_fabric_broadcast_write32(DF_MMIO_LIMIT(reg), np_top); - data_fabric_broadcast_write32(DF_MMIO_CONTROL(reg), np_ctrl.raw); - - data_fabric_print_mmio_conf(); -} diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 9dbf5da..f0073df 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -44,7 +44,6 @@ }
void data_fabric_print_mmio_conf(void); -void data_fabric_set_mmio_np(void);
enum cb_err data_fabric_get_pci_bus_numbers(struct device *domain, uint8_t *segment_group, uint8_t *first_bus, uint8_t *last_bus); diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index d3194a2..a042ea2 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -45,7 +45,6 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/chip.c b/src/soc/amd/glinda/chip.c index c8b4d08..515580d 100644 --- a/src/soc/amd/glinda/chip.c +++ b/src/soc/amd/glinda/chip.c @@ -43,7 +43,7 @@
amd_fsp_silicon_init();
- data_fabric_set_mmio_np(); + data_fabric_print_mmio_conf();
fch_init(chip_info); } diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 194b775..7f61338 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -47,7 +47,6 @@ select SOC_AMD_COMMON_BLOCK_CPU_SYNC_PSP_ADDR_MSR select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/mendocino/chip.c b/src/soc/amd/mendocino/chip.c index 99f57aa..729f97a 100644 --- a/src/soc/amd/mendocino/chip.c +++ b/src/soc/amd/mendocino/chip.c @@ -41,7 +41,7 @@
amd_fsp_silicon_init();
- data_fabric_set_mmio_np(); + data_fabric_print_mmio_conf();
fch_init(chip_info); } diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index f37dd20..0acf62b 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -42,7 +42,6 @@ select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c index b08db2b..f45e7b8 100644 --- a/src/soc/amd/phoenix/chip.c +++ b/src/soc/amd/phoenix/chip.c @@ -49,7 +49,7 @@ opensil_xSIM_timepoint_1(); }
- data_fabric_set_mmio_np(); + data_fabric_print_mmio_conf();
fch_init(chip_info); } diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 42fe66f..3768cfb 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -37,7 +37,6 @@ select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN - select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_NP_REGION select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFF select SOC_AMD_COMMON_BLOCK_GRAPHICS diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index d2070c1..7411948 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -42,7 +42,8 @@
amd_fsp_silicon_init();
- data_fabric_set_mmio_np(); + data_fabric_print_mmio_conf(); + fch_init(chip_info); }