[coreboot-gerrit] Patch merged into coreboot/master: b8fad3d arm: libpayload: Add cache coherent DMA memory definition and management

the following patch was just integrated into master:
commit b8fad3d02986222fa162d455eca2ffe807b6a15a
Author: Julius Werner 
Date:   Tue Aug 27 15:48:32 2013 -0700

arm: libpayload: Add cache coherent DMA memory definition and management

This patch adds a mechanism to set aside a region of cache-coherent
    (i.e. usually uncached) virtual memory, which can be used to communicate
    with DMA devices without automatic cache snooping (common on ARM)
    without the need of explicit flush/invalidation instructions in the
    driver code.

This works by setting aside said region in the (board-specific) page
    table setup, as exemplary done in this patch for the Snow and Pit
    boards. It uses a new mechanism for adding board-specific Coreboot table
    entries to describe this region in an entry with the LB_DMA tag.

Libpayload's memory allocator is enhanced to be able to operate on
    distinct types/regions of memory. It provides dma_malloc() and
    dma_memalign() functions for use in drivers, which by default just
    operate on the same heap as their traditional counterparts. However, if
    the Coreboot table parsing code finds a CB_DMA section, further requests
    through the dma_xxx() functions will return memory from the region
    described therein instead.

Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186
    Signed-off-by: Julius Werner 
    Reviewed-on: https://chromium-review.googlesource.com/167155
    (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01)
    Signed-off-by: Isaac Christensen 
    Reviewed-on: http://review.coreboot.org/6622
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer

See http://review.coreboot.org/6622 for details.

-gerrit