Attention is currently required from: Raul Rangel.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61086 )
Change subject: soc/amd/sabrina: add additional UART controllers
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Patch Set 5:
(1 comment)
File src/soc/amd/sabrina/Kconfig:
https://review.coreboot.org/c/coreboot/+/61086/comment/b376b3b0_b259291f
PS5, Line 241: 0xfedd1000
The PPR seems to have a typo on this address, i.e. it seems to repeat fedc_1xxx incorrectly.
oh, that's a bug in the address space mapping table in the current PPR version.
0xFEDD1000 should be the correct MMIO base address of UART4: the description of the UART registers results in that address when adding the base address to the offset to the UART4 function block and this is also what the reference code uses
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