[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/brya/vat/taeko:Disable C1E for RPL CPU

[Joey Peng (Code Review)]

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74727 )

Change subject: mb/google/brya/vat/taeko:Disable C1E for RPL CPU
......................................................................

mb/google/brya/vat/taeko:Disable C1E for RPL CPU

Disable C1E on RPL CPU for improving acoustic noise tests
We would use fw_config bit 18 to identify if the CPU is ADL or RPL

BUG=b:278654939
TEST:emerge-brya coreboot and check that C1E can be disabled on RPL SKU

Signed-off-by: Joey Peng 
Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
M src/mainboard/google/brya/variants/taeko/variant.c
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
4 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74727/1

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index cdfd2ff..67d9a35 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -42,6 +42,9 @@
    	option HPS_ABSENT			0
    	option HPS_PRESENT			1
    end
+	field C1E 18
+		option C1E_ENABLE			0
+		oprion C1E_DISABLE			1
 end
 chip soc/intel/alderlake
    register "domain_vr_config[VR_DOMAIN_IA]" = "{
diff --git a/src/mainboard/google/brya/variants/taeko/variant.c b/src/mainboard/google/brya/variants/taeko/variant.c
index b44e9e3..4b721d7 100644
--- a/src/mainboard/google/brya/variants/taeko/variant.c
+++ b/src/mainboard/google/brya/variants/taeko/variant.c
@@ -1,9 +1,24 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <fw_config.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
 #include <sar.h>

const char *get_wifi_sar_cbfs_filename(void)
 {
    return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID));
 }
+
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
+{
+        // Disable C1E for Tabor
+        if (fw_config_probe(FW_CONFIG(RPL, IS_RPL))) {
+			config->c1e = 0;
+			printk(BIOS_INFO, "Disabling C1E for RPL CPU\n");
+        }
+		else if (fw_config_probe(FW_CONFIG(RPL, NOT_RPL))){
+			config->c1e = 1;
+			printk(BIOS_INFO, "Enabling C1E for ADL CPU\n");
+		}
+}
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index c466212..969c314 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -681,6 +681,8 @@
     * Set this to 1 in order to disable Tccold Handshake
     */
    bool disable_dynamic_tccold_handshake;
+
+	uint8_t c1e;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 7789cec..d0b4876 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -1011,6 +1011,8 @@
    	s_cfg->PkgCStateDemotion = 0;
    else
    	s_cfg->PkgCStateDemotion = !config->disable_package_c_state_demotion;
+
+	s_cfg->C1e = config->c1e;
 }

static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,