Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75661?usp=email )
Change subject: soc/mediatek/mt8188: Support 4K resolution display ......................................................................
soc/mediatek/mt8188: Support 4K resolution display
The original clock rate 416MHz is insufficient for 4K resolution and causing the screen to glitch. Set the clock rate to 594MHz to support 4K resolution.
BUG=b:236328487 TEST=Glitching screen was fixed after applying this patch
Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3 Signed-off-by: Hsiao Chien Sung shawn.sung@mediatek.com Signed-off-by: Jason Chen Jason-ch.Chen@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/75661 Reviewed-by: Yidi Lin yidilin@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8188/pll.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Hsiao Chien Sung: Looks good to me, but someone else must approve
diff --git a/src/soc/mediatek/mt8188/pll.c b/src/soc/mediatek/mt8188/pll.c index 176b884..d892e1c 100644 --- a/src/soc/mediatek/mt8188/pll.c +++ b/src/soc/mediatek/mt8188/pll.c @@ -256,7 +256,7 @@ { .id = TOP_SCP_SEL, .sel = 5 }, /* 5: mainpll_d4_d2 */ { .id = TOP_BUS_AXIMEM_SEL, .sel = 1 }, /* 1: mainpll_d7_d2 */ /* CLK_CFG_1 */ - { .id = TOP_VPP_SEL, .sel = 8 }, /* 8: univpll_d6 */ + { .id = TOP_VPP_SEL, .sel = 11 }, /* 11: tvdpll1_ck */ { .id = TOP_ETHDR_SEL, .sel = 8 }, /* 8: univpll_d6 */ { .id = TOP_IPE_SEL, .sel = 8 }, /* 8: mainpll_d4_d2 */ { .id = TOP_CAM_SEL, .sel = 9 }, /* 9: mainpll_d4_d2 */