Attention is currently required from: Anil Kumar K, Bora Guvendik, Felix Held, Hannah Williams, Jamie Ryu, Subrata Banik.
Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )
Change subject: soc/intel/common/block/pmc: Add GPE1 functions ......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pmclib.h:
https://review.coreboot.org/c/coreboot/+/84104/comment/fc7d65cd_476be53f?usp... : PS11, Line 241: gpe0_mask
Adding GPE1 ref from PTL EDS links for internal device events: […]
Subrata,
Your point of decoupling GPE1 from GPE0 makes sense. However, I am not quite followed your suggestion, can you help me a bit more here? In fact, this is the only place that particularly disable PME_B0 event and then all GPE bits are disabled. I am not sure what is the reason behind and why we cannot just simply disable all GPE events. Going back to the doubt that I have on extending this 'pmc_disable_std_gpe(PME_B0_EN);' so that it can cover GPE1 portion. No STS bits was read in order to disable PME_B0. I don't find a clean/generic way to come out with mask array to disable GPE1 events and combine with the existing 32-bit GPE0 mask here for this pmc_disable_std_gpe function as an array argument.
static void smm_southbridge_enable(uint16_t pm1_events) { uint32_t smi_params = ENABLE_SMI_PARAMS;
printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events */ pmc_enable_pm1(pm1_events); pmc_disable_std_gpe(PME_B0_EN); <-
... pmc_disable_all_gpe();