[coreboot-gerrit] Change in coreboot[master]: mb/google/zork/: adjust the edp panel power sequence

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48865

to review the following change.

Change subject: mb/google/zork/: adjust the edp panel power sequence
......................................................................

mb/google/zork/: adjust the edp panel power sequence

set pwron_varybl_to_blon to 0x5, which mean fw will delay 20ms between backlight
on and vary backlight.

BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz

Signed-off-by: Chris Wang 
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
---
M src/mainboard/google/zork/variants/vilboz/overridetree.cb
1 file changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48865/1

diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
index b6a886c..11a4ef9 100644
--- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb
+++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb
@@ -29,6 +29,18 @@
    register  "edp_version" = "0x0"
    register  "edp_table_size" = "0x05"

+	# eDP power sequence. all pwr sequence numbers below are in uint of 4ms,
+	# and "0" as default vaule
+	register "edp_pwr_adjust_enable" = "1"
+	register "pwron_digon_to_De" = "0"
+	register "pwron_de_to_varybl" = "0"
+	register "pwrdown_varybloff_to_de" = "0"
+	register "pwrdown_de_to_digoff" = "0"
+	register "pwroff_delay" = "0"
+	register "pwron_varybl_to_blon" = "5"
+	register "pwrdown_bloff_to_varybloff" = "5"
+	register "min_allowed_bl_level" = "0"
+
    register "edp_tuningset" = "{
    	.dp_vs_pemph_level = 0x0,
    	.deemph_6db4 = 0x004b,