Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56594 )
Change subject: mb/siemens/mc_ehl1: Disable L1 substates for PCIe root ports ......................................................................
mb/siemens/mc_ehl1: Disable L1 substates for PCIe root ports
L1 substates of a PCIe link are meant to save some power when the link is not active but have the drawback that the PCIe latency is increased as PLLs are switched on and off as needed.
In order to get a better realtime performance, disable all substates for every PCIe root port.
Change-Id: Ic5bc8410709d0f0094810bc11a7723e88c30e397 Signed-off-by: Werner Zeh werner.zeh@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/56594 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-by: Paul Menzel paulepanter@mailbox.org --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 1eece7a..d1c5c82 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -69,6 +69,14 @@ register "PcieClkSrcClkReq[4]" = "0xFF" register "PcieClkSrcClkReq[5]" = "0xFF"
+ # Disable all L1 substates for PCIe root ports + register "PcieRpL1Substates[0]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[5]" = "L1_SS_DISABLED" + # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1"