[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/cnvi: Add CNVW OpRegion

[Matt DeVillier (Code Review)]

Attention is currently required from: Nico Huber, Sean Rhodes.

Matt DeVillier has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83556?usp=email )

Change subject: soc/intel/cnvi: Add CNVW OpRegion
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Patch Set 11: Code-Review+1

(1 comment)

File src/soc/intel/common/block/cnvi/cnvi.c:

https://review.coreboot.org/c/coreboot/+/83556/comment/93cd804c_47f03c8a?usp... :
PS6, Line 40: dev->path.pnp.port, 2
> Oh, this is PCI config space? that's confusing, there should be an ACPI […]

`GPCB() + <offset>` is used in coreboot's tcss.asl for TGL/ADL/MTL, though it would be nice to know where this offset is coming from