[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Update GPIO configuration as per schematics

[Varshit B Pandya (Code Review)]

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47495 )

Change subject: mb/intel/adlrvp: Update GPIO configuration as per schematics
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mb/intel/adlrvp: Update GPIO configuration as per schematics

Configure I2C related GPIO as per ADL-P Schematics

Signed-off-by: Varshit Pandya 
Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e
---
M src/mainboard/intel/adlrvp/gpio.c
1 file changed, 12 insertions(+), 26 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47495/1

diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index f91b94f..9f96620 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -134,22 +134,16 @@
    /* SPI_MOSI(2) */
    PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),

-	/* SPI_MIS0(0) */
-	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
    /* SPI_MIS0(1) */
    PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
    /* SPI_MIS0(2) */
    PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),

-	/* SPI_CLK(0) */
-	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
    /* SPI_CLK(1) */
    PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
    /* SPI_CLK(2) */
    PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2),

-	/*  SPI_CS(0, 0) */
-	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
    /* SPI_CS(0, 1) */
    PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
    /* SPI_CS(1, 0) */
@@ -158,34 +152,26 @@
    PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2),

/* I2C_SCL(0) */
-	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
-	/* I2C_SCL(1) */
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
-	/* I2C_SCL(2) */
    PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
-	/* I2C_SCL(3) */
+	/* I2C_SCL(1) */
    PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* I2C_SCL(2) */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+	/* I2C_SCL(3) */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
    /* I2C_SCL(5) */
-	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
-	/* I2C_SCL(6) */
-	PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1),
-	/* I2C_SCL(7) */
-	PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),

/* I2C_SDA(0) */
-	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
-	/* I2C_SDA(1) */
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
-	/* I2C_SDA(2) */
    PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
-	/* I2C_SDA(3) */
+	/* I2C_SDA(1) */
    PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* I2C_SDA(2) */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	/* I2C_SDA(3) */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
    /* I2C_SDA(5) */
-	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-	/* I2C_SDA(6) */
-	PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1),
-	/* I2C_SDA(7) */
-	PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),

/* I2S0_SCLK */
    PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),