Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44646 )
Change subject: vendorcode/google/chromeos: Introduce helper for CSE board reset
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Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom...
File src/vendorcode/google/chromeos/cse_board_reset.c:
https://review.coreboot.org/c/coreboot/+/44646/3/src/vendorcode/google/chrom...
PS3, Line 14: FULL_RST | SYS_RST
Also, usually port 0xcf9 needs time to settle between the request and the command to perform the res […]
Just setting the 4th bit is sufficient in the coreboot. This will just configure system to cold reset type which is sufficient.
```
outb(FULL_RST, RST_CNT).
```
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