[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801jx/fadt.c: Use pmutil.h definitions

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42653 )

Change subject: sb/intel/i82801jx/fadt.c: Use pmutil.h definitions
......................................................................

sb/intel/i82801jx/fadt.c: Use pmutil.h definitions

Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.

Change-Id: I572a9da0cba5d23c48c4cb06de4bb75f65f5b0b0
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/i82801jx/fadt.c
1 file changed, 9 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/42653/1

diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index 93bf599..7d025b7 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -5,6 +5,7 @@
 #include <acpi/acpi.h>
 #include <cpu/x86/smm.h>
 #include <version.h>
+#include <southbridge/intel/common/pmutil.h>
 #include "chip.h"

void acpi_fill_fadt(acpi_fadt_t *fadt)
@@ -25,11 +26,11 @@

fadt->pm1a_evt_blk = pmbase;
    fadt->pm1b_evt_blk = 0x0;
-	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
    fadt->pm1b_cnt_blk = 0x0;
-	fadt->pm2_cnt_blk = pmbase + 0x50;
-	fadt->pm_tmr_blk = pmbase + 0x8;
-	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->pm2_cnt_blk = pmbase + PM2_CNT;
+	fadt->pm_tmr_blk = pmbase + PM1_TMR;
+	fadt->gpe0_blk = pmbase + GPE0_STS;
    fadt->gpe1_blk = 0;

fadt->pm1_evt_len = 4;
@@ -87,7 +88,7 @@
    					Linux complains about 32 bit. */
    fadt->x_pm1a_cnt_blk.bit_offset = 0;
    fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
-	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT;
    fadt->x_pm1a_cnt_blk.addrh = 0x0;

fadt->x_pm1b_cnt_blk.space_id = 0;
@@ -101,21 +102,21 @@
    fadt->x_pm2_cnt_blk.bit_width = 8;
    fadt->x_pm2_cnt_blk.bit_offset = 0;
    fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
-	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT;
    fadt->x_pm2_cnt_blk.addrh = 0x0;

fadt->x_pm_tmr_blk.space_id = 1;
    fadt->x_pm_tmr_blk.bit_width = 32;
    fadt->x_pm_tmr_blk.bit_offset = 0;
    fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
    fadt->x_pm_tmr_blk.addrh = 0x0;

fadt->x_gpe0_blk.space_id = 1;
    fadt->x_gpe0_blk.bit_width = 128;
    fadt->x_gpe0_blk.bit_offset = 0;
    fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
-	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS;
    fadt->x_gpe0_blk.addrh = 0x0;

fadt->x_gpe1_blk.space_id = 0;