Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41952 )
Change subject: soc/amd: Use mp_cpu_bus_init() ......................................................................
soc/amd: Use mp_cpu_bus_init()
Change-Id: Ia4508a9a087e3996ef7667280f8e2788421e5700 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/cpu.c M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/cpu.h 6 files changed, 6 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/41952/1
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f593664..af67e07 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -22,7 +22,7 @@ struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = picasso_init_cpus, + .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, };
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 55f9014..3512c94 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -92,10 +92,10 @@ .post_mp_init = enable_smi_generation, };
-void picasso_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n");
/* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index d413c72..99b31c3 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -3,11 +3,8 @@ #ifndef __PICASSO_CPU_H__ #define __PICASSO_CPU_H__
-#include <device/device.h> - #define CSTATE_BASE_REG 0xc0010073
-void picasso_init_cpus(struct device *dev); int get_cpu_count(void); void check_mca(void);
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 41fcafb..909b847 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -25,7 +25,7 @@ struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .init = stoney_init_cpus, + .init = mp_cpu_bus_init, .acpi_fill_ssdt = generate_cpu_entries, };
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 36583a5..9189cfb 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -93,10 +93,10 @@ .post_mp_init = enable_smi_generation, };
-void stoney_init_cpus(struct device *dev) +void mp_init_cpus(struct bus *cpu_bus) { /* Clear for take-off */ - if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) + if (mp_init_with_smm(cpu_bus, &mp_ops) < 0) printk(BIOS_ERR, "MP initialization failure.\n");
/* The flash is now no longer cacheable. Reset to WP for performance. */ diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h index ea51f76..8d25fb6 100644 --- a/src/soc/amd/stoneyridge/include/soc/cpu.h +++ b/src/soc/amd/stoneyridge/include/soc/cpu.h @@ -3,8 +3,6 @@ #ifndef __STONEYRIDGE_CPU_H__ #define __STONEYRIDGE_CPU_H__
-#include <device/device.h> - /* * Set a variable MTRR in bootblock and/or romstage. AGESA will use the lowest * numbered registers. Any values defined below are subtracted from the @@ -16,7 +14,6 @@ #define SOC_EARLY_VMTRR_CAR_HEAP 2 #define SOC_EARLY_VMTRR_TEMPRAM 3
-void stoney_init_cpus(struct device *dev); void check_mca(void);
#endif /* __STONEYRIDGE_CPU_H__ */