[coreboot-gerrit] Patch merged into coreboot/master: 52a8879 pistachio: implement timer support

the following patch was just integrated into master:
commit 52a887985300cf11fbc183f6a4a4408ff9a45ec6
Author: Vadim Bendebury 
Date:   Wed Nov 5 17:50:09 2014 -0800

pistachio: implement timer support

C0_COUNT register is a free running counter clocked by the CPU
    frequency divided by two. On the FPGA board it results in 25 MHz, on
    real SOCs it will have to be figured out later.

Some magic addresses and numbers are used to find out if the code is
    running on the FPGA board.

timestamp_get() and timer_monotonic_get() are kept in the same file.

The CPU initialization makes sure that CO COUNT is in fact enabled and
    starts from zero.

BRANCH=none
    BUG=chrome-os-partner:33595,chrome-os-partner:31438
    TEST=with timer enabled, the startup code properly initializes UART
         and prints the coreboot bootblock banner message on the serial
         console.

Change-Id: I98fe330b961f677448b222917ab7d586494ed4b7
    Signed-off-by: Stefan Reinauer 
    Original-Commit-Id: a7324221c1d856ac72fa2b0ab586b5ea8cab3a05
    Original-Change-Id: I2d518213de939e91a35f8aea174aed76d297dd72
    Original-Signed-off-by: Vadim Bendebury 
    Original-Reviewed-on: https://chromium-review.googlesource.com/227888
    Original-Reviewed-by: Aaron Durbin 
    Reviewed-on: http://review.coreboot.org/9188
    Tested-by: build bot (Jenkins)
    Reviewed-by: Patrick Georgi

See http://review.coreboot.org/9188 for details.

-gerrit