HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31420 )
Change subject: SMBIOS: Update Processor Information structure to v3.2.0 ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/31420/7/src/arch/x86/smbios.c File src/arch/x86/smbios.c:
https://review.coreboot.org/#/c/31420/7/src/arch/x86/smbios.c@564 PS7, Line 564: (res.ebx >> 16) & 0xff; This is maximum number of logical processors per package, not the maximum number of cores.
Per "Intel ® Processor Identification and the CPUID Instruction" - Order Number: 241618-039
Note page #37 : "The BIOS will use this function to determine the maximum number of cores implemented in a specific physical processor package. To do this the BIOS must initially set the EAX register to 4 and the ECX register to 0 prior to executing the CPUID instruction. After executing the CPUID instruction, (EAX[31:26] + 1) contains the maximum number of cores."
I have no idea about AMD (and others) ...