Attention is currently required from: Lance Zhao, Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Kyösti Mälkki, Patrick Rudolph.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57933 )
Change subject: soc/intel: transition full control over PM Timer from FSP to coreboot
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Patch Set 33:
(1 comment)
Patchset:
PS33:
The following is from FSP header
When FALSE, it disables PCH ACPI timer, and stops TCO timer.
@note: This will have significant power impact when it's enabled.
Stopping the TCO timer is not done via the TCO registers but a result of stopping the PM timer. This is done in coreboot now (see CB:57932).
But we do have code that will stop tco timer in coreboot, only concern I have will be tco_configure() we have in common will cover tco counter 2 or not in newer silicon.
You probably mean `tco_timer_disable`? Since the timer is already stopped by disabling the PM timer, this only sets that specific disable bit for the TCO but won't have any real impact.
Regarding TCO ctr 2, I would expect it to stop, too, when the PM timer is disabled.
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