Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9319
-gerrit
commit cc6f6f6a731f2180a0a94412645947dc23e8ccd9 Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Sun Apr 5 18:10:09 2015 -0500
mainboard/lenovo/t400: Add initial hybrid graphics support
TEST: Booted T400 with Intel/ATI hybrid graphics in integrated mode with native Intel graphics init and verified integrated panel framebuffer functionality in SeaBIOS and Linux.
Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3 Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com --- src/mainboard/lenovo/t400/cmos.default | 1 + src/mainboard/lenovo/t400/cmos.layout | 10 ++- src/mainboard/lenovo/t400/romstage.c | 112 +++++++++++++++++++++++++++++++-- 3 files changed, 115 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index 1da4c7c..0fe82b7 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 57dd4d1..ad2e67e 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -1,4 +1,4 @@ -# + # # This file is part of the coreboot project. # # Copyright (C) 2007-2008 coresystems GmbH @@ -85,7 +85,10 @@ entries # coreboot config options: northbridge 939 3 e 11 gfx_uma_size
-#942 2 r 0 unused +# coreboot config options: graphics +942 2 e 12 hybrid_graphics_mode + +#944 2 r 0 unused
# coreboot config options: check sums 984 16 h 0 check_sum @@ -137,6 +140,9 @@ enumerations 11 3 128M 11 5 96M 11 6 160M +12 0 Integrated Only +12 1 Discrete Only +12 2 Switchable
# ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index f232642..f3b746a 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson tpearson@raptorengineeringinc.com, Raptor Engineering * Copyright (C) 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or @@ -38,11 +39,90 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0)
+#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 +#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 + +#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 + +static void hybrid_graphics_set_up_gpio(void) +{ + uint32_t tmp; + + // Enable hybrid graphics GPIO lines + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); + + // Set hybrid graphics control GPIO lines to output + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); + + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); + + // Set hybrid graphics detect GPIO lines to input + tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); + tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); +} + +static bool hybrid_graphics_installed(void) +{ + if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) + return false; + else + return true; +} + +static void hybrid_graphics_switch_to_integrated_graphics(void) +{ + uint32_t tmp; + + // Configure muxes + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_switch_to_discrete_graphics(void) +{ + uint32_t tmp; + + // Configure muxes + tmp = inl(DEFAULT_GPIOBASE + GP_LVL); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL); + + tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); + tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; + outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); +} + +static void hybrid_graphics_enable_switchable_graphics(void) +{ + /* Dynamic switching is handled by the OS via ACPI */ + hybrid_graphics_switch_to_integrated_graphics(); +} + static void default_southbridge_gpio_setup(void) { - outl(0x197e23fe, DEFAULT_GPIOBASE + 0x00); - outl(0xe1a66dfe, DEFAULT_GPIOBASE + 0x04); - outl(0xe3faef3f, DEFAULT_GPIOBASE + 0x0c); + outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); + outl(0xe1a66dfe, DEFAULT_GPIOBASE + GP_IO_SEL); + outl(0xe3faef3f, DEFAULT_GPIOBASE + GP_LVL);
/* Disable blink [31:0]. */ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); @@ -50,11 +130,11 @@ static void default_southbridge_gpio_setup(void) outl(0x00000102, DEFAULT_GPIOBASE + 0x2c);
/* Enable GPIOs [60:32]. */ - outl(0x030306f6, DEFAULT_GPIOBASE + 0x30); + outl(0x030306f6, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); /* Set input/output mode [60:32] (0 == out, 1 == in). */ - outl(0x1f55f9f1, DEFAULT_GPIOBASE + 0x34); + outl(0x1f55f9f1, DEFAULT_GPIOBASE + GP_IO_SEL2); /* Set gpio levels [60:32]. */ - outl(0x1dffff53, DEFAULT_GPIOBASE + 0x38); + outl(0x1dffff53, DEFAULT_GPIOBASE + GP_LVL2); }
static void early_lpc_setup(void) @@ -99,6 +179,26 @@ void main(unsigned long bist)
default_southbridge_gpio_setup();
+ /* Set up hybrid graphics GPIOs */ + hybrid_graphics_set_up_gpio(); + + if (hybrid_graphics_installed()) { + /* Select appropriate hybrid graphics device */ + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); + if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) + hybrid_graphics_switch_to_integrated_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) + hybrid_graphics_switch_to_discrete_graphics(); + else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) + hybrid_graphics_enable_switchable_graphics(); + } + else { + printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); + hybrid_graphics_switch_to_integrated_graphics(); + } + /* ASPM related setting, set early by original BIOS. */ DMIBAR16(0x204) &= ~(3 << 10);