[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable CPU PCIe in FSP

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42557 )

Change subject: soc/intel/tigerlake: Disable CPU PCIe in FSP
......................................................................

soc/intel/tigerlake: Disable CPU PCIe in FSP

In TGL SoC we have PCH and CPU side PCIe support. This patch
skips CPU side PCIe enablement in FSP if device is disabled in
devicetree. Disabling the initialization of CPU PCIe saves ~30ms
in FspSiliconInit!

BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the
boot time. FspSilicontInit time is reduced by ~30ms with this patch.

Signed-off-by: Shaunak Saha 
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/include/soc/pci_devs.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 7 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h
index 82d8360..cfb70cd 100644
--- a/src/soc/intel/tigerlake/include/soc/pci_devs.h
+++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h
@@ -34,6 +34,9 @@
 #define  SA_DEVFN_IPU		PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
 #define  SA_DEV_IPU		PCI_DEV(0, SA_DEV_SLOT_IPU, 0)

+#define SA_DEV_SLOT_CPU_PCIE	0x06
+#define  SA_DEVFN_CPU_PCIE	PCI_DEVFN(SA_DEV_SLOT_CPU_PCIE, 0)
+
 #define SA_DEV_SLOT_TBT		0x07
 #define SA_DEVFN_TBT(x)		PCI_DEVFN(SA_DEV_SLOT_TBT, (x))
 #define NUM_TBT_FUNCTIONS	4
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 4a45fd4..b12faec 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -217,6 +217,10 @@

/* Skip CPU replacement check */
    m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
+
+	/* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
+	dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
+	m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)