HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44459 )
Change subject: nb/sandybridge: Drop none reliable MCHBARx_AND_OR macro ......................................................................
nb/sandybridge: Drop none reliable MCHBARx_AND_OR macro
Use of MCHBARx_AND_OR gives an error: overflow in conversion from 'int' to 'u16' {aka 'volatile short unsigned int'} changes value from '(int)*(volatile u16 *)((unsigned int)((int)i * 1024) + 4275127072) & -65536 | 26214' to '26214' [-Werror=overflow]
Change-Id: I86e78195cd16c014e3e067edbb901756130a77ce Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 36 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/44459/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..2fe83cf 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -178,7 +178,7 @@
static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { - u32 addr, stretch; + u32 reg32, addr, stretch;
stretch = ctrl->ref_card_offset[channel]; /* @@ -190,13 +190,18 @@ stretch = 3;
addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); - printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); + reg32 = MCHBAR32(addr); + reg32 &= 0xffffc3ff; + reg32 |= ((stretch << 12) | (stretch << 10)); + printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, reg32); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); - printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); + reg32 = MCHBAR32(addr); + reg32 &= 0xfff0ffff; + reg32 |= ((stretch << 16) | (stretch << 18)); + printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, reg32); } + MCHBAR32(addr) = reg32; }
void dram_timing_regs(ramctr_timing *ctrl) @@ -3964,6 +3969,7 @@ { const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; int i, pat; + u32 reg32,
int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -3985,8 +3991,10 @@ FOR_ALL_POPULATED_CHANNELS {
/* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), - ~0x3f000000, rege3c_b24[i] << 24); + reg32 = MCHBAR32(GDCRCMDDEBUGMUXCFG_Cz_S(channel); + reg32 &= ~0x3f000000; + reg32 |= (rege3c_b24[i] << 24); + MCHBAR32(GDCRCMDDEBUGMUXCFG_Cz_S(channel) = reg32;
udelay(2);
@@ -4481,13 +4489,17 @@ int channel; int t1_cycles = 0, t1_ns = 0, t2_ns; int t3_ns; - u32 r32; + u32 r32, reg32;
/* FIXME: This register only exists on Ivy Bridge */ MCHBAR32(WMM_READ_CONFIG) = 0x46;
- FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); + FOR_ALL_CHANNELS { + reg32 = MCHBAR32(TC_OTHP_ch(channel); + reg32 &= 0xffffcfff; + reg32 |= 0x1000; + MCHBAR32(TC_OTHP_ch(channel) = reg32; + }
if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -4522,12 +4534,18 @@ }
MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); + reg32 = MCHBAR32(MEM_TRML_THRESHOLDS_CONFIG); + reg32 &= ~0x00ffffff; + reg32 |= 0x00e4d5d0; + MCHBAR32(MEM_TRML_THRESHOLDS_CONFIG) = reg32; MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f);
- FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); - + FOR_ALL_CHANNELS { + reg32 = MCHBAR32(TC_RFP_ch(channel); + reg32 &= ~(3 << 16); + reg32 |= (1 << 16); + MCHBAR32(TC_RFP_ch(channel) = reg32; + } MCHBAR32_OR(MC_INIT_STATE_G, 1); MCHBAR32_OR(MC_INIT_STATE_G, 0x80); MCHBAR32(BANDTIMERS_SNB) = 0xfa; @@ -4555,9 +4573,11 @@
/* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, - ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | + reg32 = MCHBAR32(SSKPD); + reg32 &= 0xC0C0C0C0; + reg32 |= ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); + MCHBAR32(SSKPD) = reg32; }
void restore_timings(ramctr_timing *ctrl) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 72724a3..902ed39 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -73,9 +73,6 @@ #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
/* As there are many registers, define them on a separate file */ #include "mchbar_regs.h"