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Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83789?usp=email )
Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 43:
(1 comment)
File src/soc/intel/pantherlake/acpi/gpio.asl:
https://review.coreboot.org/c/coreboot/+/83789/comment/5d231411_482511b0?usp... :
PS43, Line 259: "intc-gpio-gpi-interrupt-enable-offset",
till MTL, we were passing GPE capabilities using MISC register where not all PADs are configured as GPE.
```
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_E"
register "pmc_gpe0_dw2" = "GPP_F"
```
but looks like in PTL, each GPIO community is configuring GPE capabilities.
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