Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11066
-gerrit
commit f974cd033dd7400fa86994ddc7fa82e72b1339dc Author: Aaron Durbin adurbin@chromium.org Date: Wed Jul 22 20:42:51 2015 -0500
skylake: remove unused types and definitions in gpio.h
These types and definitions were carried over from a previous platform. However, they are not used. Remove them.
BUG=chrome-os-partner:42982 BRANCH=None TEST=Built on glados
Change-Id: Ib3d20222df34a32865aac6b6cf13517c208e17c6 Signed-off-by: Patrick Georgi pgeorgi@google.com Original-Commit-Id: be2d0d273a6c02483a944edac95ab48c433b29cd Original-Change-Id: I56a0d549f5733eec8f405f2024ced8c153fa545c Original-Signed-off-by: Aaron Durbin adurbin@chormium.org Original-Reviewed-on: https://chromium-review.googlesource.com/288191 Original-Trybot-Ready: Aaron Durbin adurbin@chromium.org Original-Tested-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-by: Robbie Zhang robbie.zhang@intel.com Original-Reviewed-by: Duncan Laurie dlaurie@chromium.org Original-Commit-Queue: Aaron Durbin adurbin@chromium.org --- src/soc/intel/skylake/include/soc/gpio.h | 139 ------------------------------- 1 file changed, 139 deletions(-)
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 03ed119..1d49a45 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -23,23 +23,6 @@
#include <stdint.h>
-/* PCH-LP GPIOBASE Registers */ -#define GPIO_OWNER(set) (0x00 + ((set) * 4)) -#define GPIO_PIRQ_APIC_EN 0x10 -#define GPIO_BLINK 0x18 -#define GPIO_SER_BLINK 0x1c -#define GPIO_SER_BLINK_CS 0x20 -#define GPIO_SER_BLINK_DATA 0x24 -#define GPIO_ROUTE(set) (0x30 + ((set) * 4)) -#define GPIO_ALT_GPI_SMI_STS 0x50 -#define GPIO_ALT_GPI_SMI_EN 0x54 -#define GPIO_RESET(set) (0x60 + ((set) * 4)) -#define GPIO_GLOBAL_CONFIG 0x7c -#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4)) -#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4)) -#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8)) -#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8)) - /* * GPP_Ax to GPP_Gx; * where x=24 [between GPIO Community A to F] @@ -148,115 +131,6 @@ typedef struct { GPIO_GET_GROUP_INDEX((pad >> 16))) #define GPIO_GET_PAD_NUMBER(pad) (pad & 0xFFFF)
-/* conf0 */ -#define GPIO_MODE_NATIVE (0 << 0) -#define GPIO_MODE_GPIO (1 << 0) - -#define GPIO_DIR_OUTPUT (0 << 2) -#define GPIO_DIR_INPUT (1 << 2) - -#define GPIO_NO_INVERT (0 << 3) -#define GPIO_INVERT (1 << 3) - -#define GPIO_IRQ_EDGE (0 << 4) -#define GPIO_IRQ_LEVEL (1 << 4) - -#define GPI_LEVEL (1 << 30) - -#define GPIO_OUT_LOW 0 -#define GPIO_OUT_HIGH 1 -#define GPO_LEVEL_SHIFT 31 -#define GPO_LEVEL_MASK (1 << GPO_LEVEL_SHIFT) -#define GPO_LEVEL_LOW (GPIO_OUT_LOW << GPO_LEVEL_SHIFT) -#define GPO_LEVEL_HIGH (GPIO_OUT_HIGH << GPO_LEVEL_SHIFT) - -/* conf1 */ -#define GPIO_PULL_NONE (0 << 0) -#define GPIO_PULL_DOWN (1 << 0) -#define GPIO_PULL_UP (2 << 0) - -#define GPIO_SENSE_ENABLE (0 << 2) -#define GPIO_SENSE_DISABLE (1 << 2) - -/* owner */ -#define GPIO_OWNER_ACPI 0 -#define GPIO_OWNER_GPIO 1 - -/* route */ -#define GPIO_ROUTE_SCI 0 -#define GPIO_ROUTE_SMI 1 - -/* irqen */ -#define GPIO_IRQ_DISABLE 0 -#define GPIO_IRQ_ENABLE 1 - -/* blink */ -#define GPO_NO_BLINK 0 -#define GPO_BLINK 1 - -/* reset */ -#define GPIO_RESET_PWROK 0 -#define GPIO_RESET_RSMRST 1 - -/* pirq route to io-apic */ - -#define GPIO_PIRQ_APIC_MASK 0 -#define GPIO_PIRQ_APIC_ROUTE 1 - -#define PCH_GPIO_END \ - { .conf0 = GPIO_LIST_END } - -#define PCH_GPIO_NATIVE \ - { .conf0 = GPIO_MODE_NATIVE } - -#define PCH_GPIO_UNUSED \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ - .owner = GPIO_OWNER_GPIO, \ - .conf1 = GPIO_SENSE_DISABLE } - -#define PCH_GPIO_ACPI_SCI \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ - .owner = GPIO_OWNER_ACPI, \ - .route = GPIO_ROUTE_SCI } - -#define PCH_GPIO_ACPI_SMI \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ - .owner = GPIO_OWNER_ACPI, \ - .route = GPIO_ROUTE_SMI } - -#define PCH_GPIO_INPUT \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ - .owner = GPIO_OWNER_GPIO } - -#define PCH_GPIO_INPUT_INVERT \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \ - .owner = GPIO_OWNER_GPIO } - -#define PCH_GPIO_IRQ_EDGE \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \ - .owner = GPIO_OWNER_GPIO, \ - .irqen = GPIO_IRQ_ENABLE } - -#define PCH_GPIO_IRQ_LEVEL \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \ - .owner = GPIO_OWNER_GPIO, \ - .irqen = GPIO_IRQ_ENABLE } - -#define PCH_GPIO_PIRQ \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \ - .owner = GPIO_OWNER_GPIO, \ - .pirq = GPIO_PIRQ_APIC_ROUTE } - -#define PCH_GPIO_OUT_HIGH \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \ - .owner = GPIO_OWNER_GPIO, \ - .conf1 = GPIO_SENSE_DISABLE } - -#define PCH_GPIO_OUT_LOW \ - { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \ - .owner = GPIO_OWNER_GPIO, \ - .conf1 = GPIO_SENSE_DISABLE } - /* Number of pins used by SerialIo controllers */ #define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 #define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 @@ -269,19 +143,6 @@ typedef struct { #define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) #define N_PCH_GPIO_PAD_MODE 10
-struct gpio_config { - u8 gpio; - u32 conf0; - u32 conf1; - u8 owner; - u8 route; - u8 irqen; - u8 reset; - u8 blink; - u8 pirq; -} __attribute__ ((packed)); - - /* For any GpioPad usage in code use GPIO_PAD type*/ typedef u32 GPIO_PAD;