Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45097 )
Change subject: soc/amd/picasso: Add emmc_config->preset_drive_strength ......................................................................
soc/amd/picasso: Add emmc_config->preset_drive_strength
This change allows passing in the preset drive strength to FSP.
BUG=b:159823235 TEST=Made sure presets are unchanged.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4 --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45097/1
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index efac418..c70de65 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -153,6 +153,24 @@ SD_EMMC_EMMC_HS400, SD_EMMC_EMMC_HS300, } timing; + + /* + * Sets the drive strength reflected in the UHS-I SDHCI Preset Value + * Registers. The drive strength is also set in the undocumented EMMCCFG + * HS400 preset register. It is not possible to read this value from the + * SDHCI Preset Value Registers. + * + * According to the SDHCI spec: + * The host should select the weakest drive strength that meets rise / + * fall time requirement at system operating frequency. + */ + enum { + SD_EMMC_DRIVE_STRENGTH_DEFAULT, + SD_EMMC_DRIVE_STRENGTH_B, + SD_EMMC_DRIVE_STRENGTH_A, + SD_EMMC_DRIVE_STRENGTH_C, + SD_EMMC_DRIVE_STRENGTH_D, + } preset_drive_strength; } emmc_config;
uint8_t xhci0_force_gen1; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 1e4f2a5..c7c3657 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -54,6 +54,8 @@ }
scfg->emmc0_mode = val; + + scfg->emmc0_drive_strength = cfg->emmc_config.preset_drive_strength; }
static void fill_dxio_descriptors(FSP_S_CONFIG *scfg,