Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, King Sumo. Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/57033
to look at the new patch set (#2).
Change subject: soc/intel/denverton_ns: Fix MRC cache write ......................................................................
soc/intel/denverton_ns: Fix MRC cache write
Fast SPI initialization is required for MRC cache write. Due to the missing initialization, the SPI transaction causes the assertion of the FCERR error bit (BIOS_HSFSTS_CTL register), so the Flash writes are failing.
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/W2E7G... Signed-off-by: King Sumo kingsumos@gmail.com Change-Id: I50cc4f8ced0b0524b39eece5a2bb4f0d99fb4eff --- M src/soc/intel/denverton_ns/bootblock/bootblock.c 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57033/2