[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N PCH

[Usha P (Code Review)]

Attention is currently required from: Reka Norman, Paul Menzel, Rizwan Qureshi, Angel Pons, Subrata Banik, Krishna P Bhat D, Usha P, Patrick Rudolph, Kangheui Won.
Hello  Felix Singer, build bot (Jenkins), Reka Norman, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Angel Pons, Subrata Banik, Sridhar Siricilla, Krishna P Bhat D, Patrick Rudolph, Kangheui Won,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/59752

to look at the new patch set (#9).

Change subject: soc/intel/alderlake: Add support for ADL-N PCH
......................................................................

soc/intel/alderlake: Add support for ADL-N PCH

Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.

Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.

Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.

Signed-off-by: Usha P 
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/include/soc/bootblock.h
2 files changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/59752/9