Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46878 )
Change subject: soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driver ......................................................................
Patch Set 41:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/sr... File src/soc/mediatek/mt8192/srclken_rc.c:
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/sr... PS41, Line 155: if (mode == INIT_MODE) { : value = ((rc_ctrl[id].dcxo_settle_blk_en & DCXO_SETTLE_BLK_EN_MSK) : << DCXO_SETTLE_BLK_EN_SHFT) : | ((rc_ctrl[id].bypass_cmd & BYPASS_CMD_EN_MSK) << BYPASS_CMD_EN_SHFT) : | ((rc_ctrl[id].sw_rc & SW_SRCLKEN_RC_MSK) << SW_SRCLKEN_RC_SHFT) : | ((rc_ctrl[id].sw_fpm & SW_SRCLKEN_FPM_MSK) << SW_SRCLKEN_FPM_SHFT) : | ((rc_ctrl[id].sw_bblpm & SW_SRCLKEN_BBLPM_MSK) : << SW_SRCLKEN_BBLPM_SHFT) : | ((rc_ctrl[id].xo_soc_link_en & XO_SOC_LINK_EN_MSK) : << XO_SOC_LINK_EN_SHFT) : | ((rc_ctrl[id].req_ack_imd_en & REQ_ACK_LOW_IMD_EN_MSK) : << REQ_ACK_LOW_IMD_EN_SHFT) : | ((rc_ctrl[id].track_en & SRCLKEN_TRACK_M_EN_MSK) : << SRCLKEN_TRACK_M_EN_SHFT) : | ((rc_ctrl[id].cnt_step & CNT_PRD_STEP_MSK) << CNT_PRD_STEP_SHFT) : | ((rc_ctrl[id].xo_prd & XO_STABLE_PRD_MSK) << XO_STABLE_PRD_SHFT) : | ((rc_ctrl[id].dcxo_prd & DCXO_STABLE_PRD_MSK) : << DCXO_STABLE_PRD_SHFT); : } else if (mode == SW_MODE) { : value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) | (0x1 << SW_SRCLKEN_RC_SHFT); : } else if (mode == HW_MODE) { : value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) : & ~(SW_SRCLKEN_RC_MSK << SW_SRCLKEN_RC_SHFT); : } else : return; : : write32(&rc_regs->rc_mxx_srclken_cfg[id], value); SET32_BITFIELDS
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/sr... PS41, Line 194: if (mode == SW_FPM_HIGH) : value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) | (0x1 << SW_SRCLKEN_FPM_SHFT); : else if (mode == SW_FPM_LOW) : value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) : & ~(SW_SRCLKEN_FPM_MSK << SW_SRCLKEN_FPM_SHFT); : else : return; : : rc_ctrl[id].sw_fpm = mode; : write32(&rc_regs->rc_mxx_srclken_cfg[id], value); SET32_BITFIELDS
https://review.coreboot.org/c/coreboot/+/46878/41/src/soc/mediatek/mt8192/sr... PS41, Line 214: if (mode == SW_BBLPM_HIGH) : value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) : | (0x1 << SW_SRCLKEN_BBLPM_SHFT); : else if (mode == SW_BBLPM_LOW) : value = read32(&rc_regs->rc_mxx_srclken_cfg[id]) : & ~(SW_SRCLKEN_BBLPM_MSK << SW_SRCLKEN_BBLPM_SHFT); : else : return; : : rc_ctrl[id].sw_bblpm = mode; : write32(&rc_regs->rc_mxx_srclken_cfg[id], value); ditto