[coreboot-gerrit] Change in coreboot[master]: cpu/amd/agesa/family15tn/model_15_init.c: create correct MTRR solution

[Arthur Heymans (Code Review)]

Attention is currently required from: Michał Żygowski, Angel Pons, Felix Held.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53991 )

Change subject: cpu/amd/agesa/family15tn/model_15_init.c: create correct MTRR solution
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Patch Set 3:

(1 comment)

File src/cpu/amd/agesa/family15tn/model_15_init.c:

https://review.coreboot.org/c/coreboot/+/53991/comment/8525fc21_03b3d168 
PS3, Line 39: execution
> `AGESA execution`?
>
> I was wondering why Intel platforms don't need this. I suppose it's because AGESA is executed in-place, as opposed to post-RAM coreboot stages and blobs (refcode, FSP-S).

Ramstage is not executed in place. Caching the ROM is not needed at this point.