[coreboot-gerrit] Change in coreboot[master]: mb/ocp/monolake: Configure IPMI BMC FRB2 watchdog timer via VPD varia...

[Johnny Lin (Code Review)]

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36180 )

Change subject: mb/ocp/monolake: Configure IPMI BMC FRB2 watchdog timer via VPD variables
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mb/ocp/monolake: Configure IPMI BMC FRB2 watchdog timer via VPD variables

Add VPD variables for enabling/disabling FRB2 watchdog timer and
setting the timer countdown value. By default it would start the
timer and trigger hard reset when it's expired. The timer is
expected to be stopped later by payload or OS.
Right now the timer is started after FSP-M. Ideally it should be
before FSP-M (to detect memory training error).

Tested on OCP Mono Lake.

Change-Id: I82b244d08380a0461c92662e025d8b95b3133e23
Signed-off-by: Johnny Lin 
---
M src/mainboard/ocp/monolake/ipmi.c
M src/mainboard/ocp/monolake/ipmi.h
2 files changed, 1 insertion(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36180/1

diff --git a/src/mainboard/ocp/monolake/ipmi.c b/src/mainboard/ocp/monolake/ipmi.c
index 37aacc8..3f178dc 100644
--- a/src/mainboard/ocp/monolake/ipmi.c
+++ b/src/mainboard/ocp/monolake/ipmi.c
@@ -17,8 +17,6 @@
 #include <console/console.h>
 #include "ipmi.h"

-#define BMC_KCS_BASE 0xca2
-
 int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp)
 {
    int ret;
diff --git a/src/mainboard/ocp/monolake/ipmi.h b/src/mainboard/ocp/monolake/ipmi.h
index 5863eb5..0464911 100644
--- a/src/mainboard/ocp/monolake/ipmi.h
+++ b/src/mainboard/ocp/monolake/ipmi.h
@@ -23,7 +23,7 @@
 #define GET_CMOS_BIT(x) ((x) & (1 << 1))
 #define GET_VALID_BIT(x) ((x) & (1 << 7))
 #define CLEAR_CMOS_AND_VALID_BIT(x) ((x) &= 0x7d)
-
+#define BMC_KCS_BASE 0xca2
 typedef struct {
    u8 BootMode; /* Bit 1:CMOS clear, bit 7:valid bit. */
    u8 Boot0000;